[llvm] f90f0e8 - [AMDGPU][GFX10][DOC][NFC] Update assembler syntax description
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 4 03:31:15 PDT 2022
Author: Dmitry Preobrazhensky
Date: 2022-07-04T13:30:56+03:00
New Revision: f90f0e8fe7f552cab14e8b6e008b01738f11568e
URL: https://github.com/llvm/llvm-project/commit/f90f0e8fe7f552cab14e8b6e008b01738f11568e
DIFF: https://github.com/llvm/llvm-project/commit/f90f0e8fe7f552cab14e8b6e008b01738f11568e.diff
LOG: [AMDGPU][GFX10][DOC][NFC] Update assembler syntax description
Summary of changes:
- Update MUBUF lds syntax (see https://reviews.llvm.org/D124485).
- Add v_cvt_pkrtz_f16_f32_dpp, v_cvt_pkrtz_f16_f32_sdwa.
- Update SMEM syntax (see https://reviews.llvm.org/D127314).
- Enable op_sel for v_add_nc_u16, v_sub_nc_u16 (see https://reviews.llvm.org/D123594).
- Minor bug fixing and improvements.
Added:
llvm/docs/AMDGPU/gfx10_opt_0d447d.rst
llvm/docs/AMDGPU/gfx10_opt_847aed.rst
llvm/docs/AMDGPU/gfx10_soffset_73dae7.rst
llvm/docs/AMDGPU/gfx10_soffset_d01a5c.rst
llvm/docs/AMDGPU/gfx10_vdata_0aba12.rst
llvm/docs/AMDGPU/gfx10_vdata_16d321.rst
llvm/docs/AMDGPU/gfx10_vdata_35851e.rst
llvm/docs/AMDGPU/gfx10_vdata_890652.rst
llvm/docs/AMDGPU/gfx10_vdata_a9ff5a.rst
llvm/docs/AMDGPU/gfx10_vdst_2ea017.rst
llvm/docs/AMDGPU/gfx10_vdst_322561.rst
llvm/docs/AMDGPU/gfx10_vdst_709347.rst
llvm/docs/AMDGPU/gfx10_vdst_81a6ed.rst
llvm/docs/AMDGPU/gfx10_vdst_d71f1c.rst
llvm/docs/AMDGPU/gfx10_vdst_dd8a32.rst
Modified:
llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst
llvm/docs/AMDGPU/gfx10_hwreg.rst
Removed:
llvm/docs/AMDGPU/gfx10_opt.rst
llvm/docs/AMDGPU/gfx10_soffset_59fade.rst
llvm/docs/AMDGPU/gfx10_soffset_c40a5a.rst
llvm/docs/AMDGPU/gfx10_vdata_325b78.rst
llvm/docs/AMDGPU/gfx10_vdata_4d8ecf.rst
llvm/docs/AMDGPU/gfx10_vdata_87fb90.rst
llvm/docs/AMDGPU/gfx10_vdata_b2a787.rst
llvm/docs/AMDGPU/gfx10_vdata_c61803.rst
llvm/docs/AMDGPU/gfx10_vdst_48d3a8.rst
llvm/docs/AMDGPU/gfx10_vdst_5d50a1.rst
llvm/docs/AMDGPU/gfx10_vdst_719833.rst
llvm/docs/AMDGPU/gfx10_vdst_a49b76.rst
llvm/docs/AMDGPU/gfx10_vdst_d7c57e.rst
llvm/docs/AMDGPU/gfx10_vdst_f47754.rst
################################################################################
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst
index ec7ff6da472e8..3dc17cc4c9145 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst
@@ -36,106 +36,107 @@ DPP16
.. parsed-literal::
- **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- v_add_co_ci_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_add_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_add_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_add_nc_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_and_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_ashrrev_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_bfrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_ceil_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_ceil_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cndmask_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cos_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cos_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_f16_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_f16_i16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_f16_u16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_f32_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_f32_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_f32_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_f32_ubyte0_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_f32_ubyte1_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_f32_ubyte2_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_f32_ubyte3_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_flr_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_norm_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_norm_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_off_f32_i4_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_rpi_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_u32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_exp_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_exp_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_ffbh_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_ffbh_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_ffbl_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_floor_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_floor_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_fmac_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_fmac_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_fract_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_fract_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_frexp_exp_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_frexp_exp_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_frexp_mant_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_frexp_mant_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_ldexp_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`i16<amdgpu_synid_gfx10_type_deviation>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_log_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_log_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_lshlrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_lshrrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_mac_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_max_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_max_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_max_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_max_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_min_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_min_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_min_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_min_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_mov_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_movreld_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_movrels_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_movrelsd_2_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_movrelsd_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_mul_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_mul_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_mul_hi_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_mul_hi_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_mul_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_mul_legacy_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_mul_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_not_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_or_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_rcp_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_rcp_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_rcp_iflag_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_rndne_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_rndne_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_rsq_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_rsq_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_sat_pk_u8_i16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_sin_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_sin_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_sqrt_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_sqrt_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_sub_co_ci_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_sub_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_sub_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_sub_nc_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_subrev_co_ci_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_subrev_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_subrev_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_subrev_nc_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_trunc_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_trunc_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_xnor_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_xor_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add_co_ci_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_add_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_add_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_add_nc_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_and_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ashrrev_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_bfrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ceil_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ceil_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cndmask_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cos_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cos_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f16_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f16_i16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f16_u16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_ubyte0_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_ubyte1_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_ubyte2_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_ubyte3_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_flr_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_norm_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_norm_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_off_f32_i4_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_pkrtz_f16_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_rpi_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_u32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_exp_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_exp_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ffbh_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ffbh_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ffbl_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_floor_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_floor_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_fmac_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_fmac_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_fract_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_fract_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_frexp_exp_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_frexp_exp_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_frexp_mant_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_frexp_mant_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ldexp_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`i16<amdgpu_synid_gfx10_type_deviation>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_log_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_log_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_lshlrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_lshrrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mac_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_max_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_max_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_max_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_max_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_min_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_min_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_min_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_min_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mov_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_movreld_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_movrels_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_movrelsd_2_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_movrelsd_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_hi_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_hi_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_legacy_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_not_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_or_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rcp_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rcp_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rcp_iflag_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rndne_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rndne_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rsq_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rsq_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sat_pk_u8_i16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sin_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sin_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sqrt_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sqrt_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sub_co_ci_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sub_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sub_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sub_nc_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_subrev_co_ci_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_subrev_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_subrev_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_subrev_nc_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_trunc_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_trunc_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_xnor_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_xor_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
DPP8
----
@@ -172,6 +173,7 @@ DPP8
v_cvt_norm_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
v_cvt_norm_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
v_cvt_off_f32_i4_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_pkrtz_f16_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
v_cvt_rpi_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
v_cvt_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
v_cvt_u32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
@@ -421,38 +423,38 @@ FLAT
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
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- flat_atomic_add :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_add_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_and :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_and_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_cmpswap :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_e016a1>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_dec :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_dec_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_fcmpswap :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`f32x2<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_fcmpswap_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_e016a1>`::ref:`f64x2<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_fmax :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_fmax_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_fmin :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_fmin_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_inc :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_inc_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_or :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_or_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_smax :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_smax_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_smin :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_smin_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_sub :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_sub_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_swap :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_swap_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_umax :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_umax_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_umin :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_umin_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_xor :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_atomic_xor_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_add :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_add_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_and :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_and_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_cmpswap :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_e016a1>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_dec :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_dec_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_fcmpswap :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`f32x2<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_fcmpswap_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_e016a1>`::ref:`f64x2<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_fmax :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_fmax_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_fmin :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_fmin_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_inc :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_inc_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_or :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_or_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_smax :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_smax_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_smin :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_smin_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_sub :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_sub_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_swap :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_swap_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_umax :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_umax_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_umin :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_umin_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_xor :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_xor_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_load_dword :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx10_vdst_48e42f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
@@ -475,38 +477,38 @@ FLAT
flat_store_dwordx4 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_e016a1>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_store_short :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
flat_store_short_d16_hi :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_add :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_add_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_and :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_and_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_cmpswap :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_e016a1>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_dec :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_dec_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_fcmpswap :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`f32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_fcmpswap_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_e016a1>`::ref:`f64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_fmax :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_fmax_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_fmin :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_fmin_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_inc :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_inc_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_or :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_or_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_smax :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_smax_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_smin :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_smin_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_sub :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_sub_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_swap :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_swap_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_umax :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_umax_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_umin :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_umin_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_xor :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_xor_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_add :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_add_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_and :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_and_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_cmpswap :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_e016a1>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_dec :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_dec_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_fcmpswap :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`f32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_fcmpswap_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_e016a1>`::ref:`f64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_fmax :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_fmax_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_fmin :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_fmin_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_inc :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_inc_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_or :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_or_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_smax :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_smax_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_smin :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_smin_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_sub :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_sub_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_swap :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_swap_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_umax :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_umax_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_umin :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_umin_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_xor :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_xor_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt_847aed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_load_dword :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
global_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx10_vdst_48e42f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
@@ -559,46 +561,46 @@ MIMG
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- image_atomic_add :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_and :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_cmpswap :ref:`vdata<amdgpu_synid_gfx10_vdata_4d8ecf>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_dec :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_fcmpswap :ref:`vdata<amdgpu_synid_gfx10_vdata_4d8ecf>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_fmax :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_fmin :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_inc :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_or :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_smax :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_smin :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_sub :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_swap :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_umax :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_umin :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_xor :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_gather4 :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_b :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_b_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_b_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_b_o :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_b :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_b_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_b_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_b_o :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_l :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_l_o :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_lz :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_lz_o :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_o :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_l :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_l_o :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_lz :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_lz_o :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_o :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_atomic_add :ref:`vdata<amdgpu_synid_gfx10_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_and :ref:`vdata<amdgpu_synid_gfx10_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_cmpswap :ref:`vdata<amdgpu_synid_gfx10_vdata_a9ff5a>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_dec :ref:`vdata<amdgpu_synid_gfx10_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_fcmpswap :ref:`vdata<amdgpu_synid_gfx10_vdata_a9ff5a>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_fmax :ref:`vdata<amdgpu_synid_gfx10_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_fmin :ref:`vdata<amdgpu_synid_gfx10_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_inc :ref:`vdata<amdgpu_synid_gfx10_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_or :ref:`vdata<amdgpu_synid_gfx10_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_smax :ref:`vdata<amdgpu_synid_gfx10_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_smin :ref:`vdata<amdgpu_synid_gfx10_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_sub :ref:`vdata<amdgpu_synid_gfx10_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_swap :ref:`vdata<amdgpu_synid_gfx10_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_umax :ref:`vdata<amdgpu_synid_gfx10_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_umin :ref:`vdata<amdgpu_synid_gfx10_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_xor :ref:`vdata<amdgpu_synid_gfx10_vdata_35851e>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_gather4 :ref:`vdst<amdgpu_synid_gfx10_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_b :ref:`vdst<amdgpu_synid_gfx10_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_b_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_b_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_b_o :ref:`vdst<amdgpu_synid_gfx10_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c :ref:`vdst<amdgpu_synid_gfx10_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_b :ref:`vdst<amdgpu_synid_gfx10_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_b_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_b_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_b_o :ref:`vdst<amdgpu_synid_gfx10_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_l :ref:`vdst<amdgpu_synid_gfx10_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_l_o :ref:`vdst<amdgpu_synid_gfx10_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_lz :ref:`vdst<amdgpu_synid_gfx10_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_lz_o :ref:`vdst<amdgpu_synid_gfx10_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_o :ref:`vdst<amdgpu_synid_gfx10_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_l :ref:`vdst<amdgpu_synid_gfx10_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_l_o :ref:`vdst<amdgpu_synid_gfx10_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_lz :ref:`vdst<amdgpu_synid_gfx10_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_lz_o :ref:`vdst<amdgpu_synid_gfx10_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_o :ref:`vdst<amdgpu_synid_gfx10_vdst_2ea017>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
image_get_lod :ref:`vdst<amdgpu_synid_gfx10_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
image_get_resinfo :ref:`vdst<amdgpu_synid_gfx10_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
image_load :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
@@ -675,14 +677,14 @@ MTBUF
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- tbuffer_load_format_d16_x :ref:`vdst<amdgpu_synid_gfx10_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- tbuffer_load_format_d16_xy :ref:`vdst<amdgpu_synid_gfx10_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- tbuffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid_gfx10_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- tbuffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid_gfx10_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- tbuffer_load_format_x :ref:`vdst<amdgpu_synid_gfx10_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- tbuffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx10_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- tbuffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx10_vdst_a49b76>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- tbuffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx10_vdst_f47754>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ tbuffer_load_format_d16_x :ref:`vdst<amdgpu_synid_gfx10_vdst_709347>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ tbuffer_load_format_d16_xy :ref:`vdst<amdgpu_synid_gfx10_vdst_709347>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ tbuffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid_gfx10_vdst_d71f1c>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ tbuffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid_gfx10_vdst_d71f1c>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ tbuffer_load_format_x :ref:`vdst<amdgpu_synid_gfx10_vdst_709347>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ tbuffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx10_vdst_d71f1c>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ tbuffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx10_vdst_81a6ed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ tbuffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx10_vdst_dd8a32>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
tbuffer_store_format_d16_x :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
tbuffer_store_format_d16_xy :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
tbuffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
@@ -697,80 +699,80 @@ MUBUF
.. parsed-literal::
- **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- buffer_atomic_add :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_add_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_and :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_and_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_cmpswap :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_cmpswap_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_87fb90>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_dec :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_dec_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_fcmpswap :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_fcmpswap_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_87fb90>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_fmax :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_fmax_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_fmin :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_fmin_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_inc :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_inc_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_or :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_or_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_smax :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_smax_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_smin :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_smin_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_sub :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_sub_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_swap :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_swap_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_umax :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_umax_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_umin :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_umin_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_xor :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_xor_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ buffer_atomic_add :ref:`vdata<amdgpu_synid_gfx10_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_add_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_and :ref:`vdata<amdgpu_synid_gfx10_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_and_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_cmpswap :ref:`vdata<amdgpu_synid_gfx10_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_cmpswap_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_890652>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_dec :ref:`vdata<amdgpu_synid_gfx10_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_dec_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_fcmpswap :ref:`vdata<amdgpu_synid_gfx10_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_fcmpswap_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_890652>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_fmax :ref:`vdata<amdgpu_synid_gfx10_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_fmax_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_fmin :ref:`vdata<amdgpu_synid_gfx10_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_fmin_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_inc :ref:`vdata<amdgpu_synid_gfx10_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_inc_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_or :ref:`vdata<amdgpu_synid_gfx10_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_or_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smax :ref:`vdata<amdgpu_synid_gfx10_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smax_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smin :ref:`vdata<amdgpu_synid_gfx10_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smin_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_sub :ref:`vdata<amdgpu_synid_gfx10_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_sub_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_swap :ref:`vdata<amdgpu_synid_gfx10_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_swap_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umax :ref:`vdata<amdgpu_synid_gfx10_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umax_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umin :ref:`vdata<amdgpu_synid_gfx10_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umin_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_xor :ref:`vdata<amdgpu_synid_gfx10_vdata_0aba12>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_xor_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_16d321>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_gl0_inv
buffer_gl1_inv
- buffer_load_dword :ref:`vdst<amdgpu_synid_gfx10_vdst_719833>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx10_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx10_vdst_a49b76>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx10_vdst_f47754>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_format_d16_x :ref:`vdst<amdgpu_synid_gfx10_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_format_d16_xy :ref:`vdst<amdgpu_synid_gfx10_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid_gfx10_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid_gfx10_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_format_x :ref:`vdst<amdgpu_synid_gfx10_vdst_719833>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx10_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx10_vdst_a49b76>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx10_vdst_f47754>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_sbyte :ref:`vdst<amdgpu_synid_gfx10_vdst_719833>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_short_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_sshort :ref:`vdst<amdgpu_synid_gfx10_vdst_719833>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_ubyte :ref:`vdst<amdgpu_synid_gfx10_vdst_719833>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_ushort :ref:`vdst<amdgpu_synid_gfx10_vdst_719833>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_store_byte :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_byte_d16_hi :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_dword :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_dwordx2 :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_dwordx3 :ref:`vdata<amdgpu_synid_gfx10_vdata_56f215>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_dwordx4 :ref:`vdata<amdgpu_synid_gfx10_vdata_e016a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_d16_x :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_d16_xy :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_d16_xyzw :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_x :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_xy :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_xyz :ref:`vdata<amdgpu_synid_gfx10_vdata_56f215>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_xyzw :ref:`vdata<amdgpu_synid_gfx10_vdata_e016a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_short :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_short_d16_hi :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_dword :ref:`vdst<amdgpu_synid_gfx10_vdst_322561>`::ref:`opt<amdgpu_synid_gfx10_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx10_vdst_d71f1c>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx10_vdst_81a6ed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx10_vdst_dd8a32>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_d16_x :ref:`vdst<amdgpu_synid_gfx10_vdst_709347>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_d16_xy :ref:`vdst<amdgpu_synid_gfx10_vdst_709347>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid_gfx10_vdst_d71f1c>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid_gfx10_vdst_d71f1c>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_x :ref:`vdst<amdgpu_synid_gfx10_vdst_322561>`::ref:`opt<amdgpu_synid_gfx10_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx10_vdst_d71f1c>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx10_vdst_81a6ed>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx10_vdst_dd8a32>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_sbyte :ref:`vdst<amdgpu_synid_gfx10_vdst_322561>`::ref:`opt<amdgpu_synid_gfx10_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst_709347>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst_709347>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_short_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst_709347>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst_709347>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_sshort :ref:`vdst<amdgpu_synid_gfx10_vdst_322561>`::ref:`opt<amdgpu_synid_gfx10_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_ubyte :ref:`vdst<amdgpu_synid_gfx10_vdst_322561>`::ref:`opt<amdgpu_synid_gfx10_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst_709347>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst_709347>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_ushort :ref:`vdst<amdgpu_synid_gfx10_vdst_322561>`::ref:`opt<amdgpu_synid_gfx10_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_store_byte :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_byte_d16_hi :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dword :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx2 :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx3 :ref:`vdata<amdgpu_synid_gfx10_vdata_56f215>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx4 :ref:`vdata<amdgpu_synid_gfx10_vdata_e016a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_x :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_xy :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_xyzw :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_x :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xy :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xyz :ref:`vdata<amdgpu_synid_gfx10_vdata_56f215>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xyzw :ref:`vdata<amdgpu_synid_gfx10_vdata_e016a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_short :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_short_d16_hi :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
SDWA
----
@@ -930,7 +932,8 @@ SDWA
v_cvt_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cvt_norm_i16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cvt_norm_u16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_off_f32_i4_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_off_f32_i4_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_pkrtz_f16_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
v_cvt_rpi_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cvt_u16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cvt_u32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
@@ -1005,91 +1008,91 @@ SMEM
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- s_atc_probe :ref:`probe<amdgpu_synid_gfx10_probe>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>`
- s_atc_probe_buffer :ref:`probe<amdgpu_synid_gfx10_probe>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>`
- s_atomic_add :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_add_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_and :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_and_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_cmpswap :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_c6aec1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_dec :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_dec_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_inc :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_inc_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_or :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_or_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_smax :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_smax_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_smin :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_smin_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_sub :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_sub_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_swap :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_swap_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_umax :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_umax_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_umin :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_umin_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_xor :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_xor_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_add :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_add_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_and :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_and_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_cmpswap :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_c6aec1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_dec :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_dec_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_inc :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_inc_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_or :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_or_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_smax :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_smax_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_smin :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_smin_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_sub :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_sub_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_swap :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_swap_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_umax :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_umax_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_umin :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_umin_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_xor :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_xor_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_load_dword :ref:`sdst<amdgpu_synid_gfx10_sdst_54e16e>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
- s_buffer_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx10_sdst_3bc700>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
- s_buffer_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
- s_buffer_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx10_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
- s_buffer_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx10_sdst_362c37>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
- s_buffer_store_dword :ref:`sdata<amdgpu_synid_gfx10_sdata_6fbc49>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx10_sdata_81ba27>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx10_sdata_7cbd60>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
- s_dcache_discard :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>`
- s_dcache_discard_x2 :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>`
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_atc_probe :ref:`probe<amdgpu_synid_gfx10_probe>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>`
+ s_atc_probe_buffer :ref:`probe<amdgpu_synid_gfx10_probe>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>`
+ s_atomic_add :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_add_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_and :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_and_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_cmpswap :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_c6aec1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_dec :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_dec_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_inc :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_inc_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_or :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_or_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smax :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smax_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smin :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smin_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_sub :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_sub_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_swap :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_swap_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umax :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umax_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umin :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umin_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_xor :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_xor_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_add :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_add_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_and :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_and_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_cmpswap :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_c6aec1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_dec :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_dec_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_inc :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_inc_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_or :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_or_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smax :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smax_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smin :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smin_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_sub :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_sub_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_swap :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_swap_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umax :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umax_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umin :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umin_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_xor :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_xor_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_load_dword :ref:`sdst<amdgpu_synid_gfx10_sdst_54e16e>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_buffer_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx10_sdst_3bc700>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_buffer_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_buffer_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx10_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_buffer_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx10_sdst_362c37>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_buffer_store_dword :ref:`sdata<amdgpu_synid_gfx10_sdata_6fbc49>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx10_sdata_81ba27>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx10_sdata_7cbd60>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_d01a5c>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_dcache_discard :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>`
+ s_dcache_discard_x2 :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>`
s_dcache_inv
s_dcache_wb
s_get_waveid_in_workgroup :ref:`sdst<amdgpu_synid_gfx10_sdst_54e16e>`
s_gl1_inv
- s_load_dword :ref:`sdst<amdgpu_synid_gfx10_sdst_54e16e>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
- s_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx10_sdst_3bc700>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
- s_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
- s_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx10_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
- s_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx10_sdst_362c37>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_load_dword :ref:`sdst<amdgpu_synid_gfx10_sdst_54e16e>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx10_sdst_3bc700>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx10_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx10_sdst_362c37>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
s_memrealtime :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`::ref:`b64<amdgpu_synid_gfx10_type_deviation>`
s_memtime :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`::ref:`b64<amdgpu_synid_gfx10_type_deviation>`
- s_scratch_load_dword :ref:`sdst<amdgpu_synid_gfx10_sdst_54e16e>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_b2d796>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
- s_scratch_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_b2d796>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
- s_scratch_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx10_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_b2d796>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
- s_scratch_store_dword :ref:`sdata<amdgpu_synid_gfx10_sdata_6fbc49>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_b2d796>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_scratch_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx10_sdata_81ba27>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_b2d796>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_scratch_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx10_sdata_7cbd60>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_b2d796>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_store_dword :ref:`sdata<amdgpu_synid_gfx10_sdata_6fbc49>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx10_sdata_81ba27>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
- s_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx10_sdata_7cbd60>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_load_dword :ref:`sdst<amdgpu_synid_gfx10_sdst_54e16e>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_b2d796>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_scratch_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_b2d796>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_scratch_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx10_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_b2d796>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_scratch_store_dword :ref:`sdata<amdgpu_synid_gfx10_sdata_6fbc49>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_b2d796>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx10_sdata_81ba27>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_b2d796>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx10_sdata_7cbd60>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_b2d796>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_store_dword :ref:`sdata<amdgpu_synid_gfx10_sdata_6fbc49>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx10_sdata_81ba27>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx10_sdata_7cbd60>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_73dae7>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
SOP1
----
@@ -1501,7 +1504,7 @@ VOP3
v_add_lshl_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`
v_add_nc_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
v_add_nc_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
- v_add_nc_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_nc_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
v_add_nc_u32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
v_alignbit_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_c27036>`::ref:`b16<amdgpu_synid_gfx10_type_deviation>`
v_alignbyte_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_c27036>`::ref:`b16<amdgpu_synid_gfx10_type_deviation>`
@@ -1903,7 +1906,7 @@ VOP3
v_sub_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_sub_nc_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
v_sub_nc_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sub_nc_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_nc_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
v_sub_nc_u32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
v_subrev_co_ci_u32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`ssrc2<amdgpu_synid_gfx10_ssrc_3ec588>` :ref:`clamp<amdgpu_synid_clamp>`
v_subrev_co_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
@@ -2163,7 +2166,8 @@ VOPC
gfx10_m_254bcb
gfx10_m_f5d306
gfx10_msg
- gfx10_opt
+ gfx10_opt_0d447d
+ gfx10_opt_847aed
gfx10_param
gfx10_probe
gfx10_saddr_beaa25
@@ -2189,9 +2193,9 @@ VOPC
gfx10_simm32_6f0844
gfx10_simm32_a3e80c
gfx10_simm32_be0c1c
- gfx10_soffset_59fade
+ gfx10_soffset_73dae7
gfx10_soffset_b556e6
- gfx10_soffset_c40a5a
+ gfx10_soffset_d01a5c
gfx10_src_37d670
gfx10_src_516946
gfx10_src_823582
@@ -2225,31 +2229,31 @@ VOPC
gfx10_vdata0_fd235e
gfx10_vdata1_6802ce
gfx10_vdata1_fd235e
+ gfx10_vdata_0aba12
gfx10_vdata_15d255
- gfx10_vdata_325b78
- gfx10_vdata_4d8ecf
+ gfx10_vdata_16d321
+ gfx10_vdata_35851e
gfx10_vdata_56f215
gfx10_vdata_6802ce
- gfx10_vdata_87fb90
- gfx10_vdata_b2a787
+ gfx10_vdata_890652
+ gfx10_vdata_a9ff5a
gfx10_vdata_c08393
- gfx10_vdata_c61803
gfx10_vdata_e016a1
gfx10_vdata_fd235e
+ gfx10_vdst_2ea017
+ gfx10_vdst_322561
gfx10_vdst_3d7dcf
gfx10_vdst_463513
gfx10_vdst_473a69
- gfx10_vdst_48d3a8
gfx10_vdst_48e42f
- gfx10_vdst_5d50a1
gfx10_vdst_69a144
- gfx10_vdst_719833
+ gfx10_vdst_709347
+ gfx10_vdst_81a6ed
gfx10_vdst_89680f
- gfx10_vdst_a49b76
gfx10_vdst_bdb32f
gfx10_vdst_d0dc43
- gfx10_vdst_d7c57e
- gfx10_vdst_f47754
+ gfx10_vdst_d71f1c
+ gfx10_vdst_dd8a32
gfx10_vsrc_533a4e
gfx10_vsrc_6802ce
gfx10_vsrc_e016a1
diff --git a/llvm/docs/AMDGPU/gfx10_hwreg.rst b/llvm/docs/AMDGPU/gfx10_hwreg.rst
index c7c821ab2fff8..ccfa97d53c3e0 100644
--- a/llvm/docs/AMDGPU/gfx10_hwreg.rst
+++ b/llvm/docs/AMDGPU/gfx10_hwreg.rst
@@ -41,27 +41,27 @@ or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
Defined register *names* include:
- ==================== ==========================================
- Name Description
- ==================== ==========================================
- HW_REG_MODE Shader writeable mode bits.
- HW_REG_STATUS Shader read-only status.
- HW_REG_TRAPSTS Trap status.
- HW_REG_HW_ID1 Id of wave, simd, compute unit, etc.
- HW_REG_HW_ID2 Id of queue, pipeline, etc.
- HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
- HW_REG_LDS_ALLOC Per-wave LDS allocation.
- HW_REG_IB_STS Counters of outstanding instructions.
- HW_REG_SH_MEM_BASES Memory aperture.
- HW_REG_TBA_LO tba_lo register.
- HW_REG_TBA_HI tba_hi register.
- HW_REG_TMA_LO tma_lo register.
- HW_REG_TMA_HI tma_hi register.
- HW_REG_FLAT_SCR_LO flat_scratch_lo register.
- HW_REG_FLAT_SCR_HI flat_scratch_hi register.
- HW_REG_XNACK_MASK xnack_mask register.
- HW_REG_POPS_PACKER pops_packer register.
- ==================== ==========================================
+ ============================== ==========================================
+ Name Description
+ ============================== ==========================================
+ HW_REG_MODE Shader writeable mode bits.
+ HW_REG_STATUS Shader read-only status.
+ HW_REG_TRAPSTS Trap status.
+ HW_REG_HW_ID1 Id of wave, simd, compute unit, etc.
+ HW_REG_HW_ID2 Id of queue, pipeline, etc.
+ HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
+ HW_REG_LDS_ALLOC Per-wave LDS allocation.
+ HW_REG_IB_STS Counters of outstanding instructions.
+ HW_REG_SH_MEM_BASES Memory aperture.
+ HW_REG_TBA_LO tba_lo register.
+ HW_REG_TBA_HI tba_hi register.
+ HW_REG_TMA_LO tma_lo register.
+ HW_REG_TMA_HI tma_hi register.
+ HW_REG_FLAT_SCR_LO flat_scratch_lo register.
+ HW_REG_FLAT_SCR_HI flat_scratch_hi register.
+ HW_REG_XNACK_MASK xnack_mask register.
+ HW_REG_POPS_PACKER pops_packer register.
+ ============================== ==========================================
Examples:
diff --git a/llvm/docs/AMDGPU/gfx10_opt_0d447d.rst b/llvm/docs/AMDGPU/gfx10_opt_0d447d.rst
new file mode 100644
index 0000000000000..8516a94a3fdc8
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_opt_0d447d.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx10_opt_0d447d:
+
+opt
+===
+
+This is an optional operand. It must be used if and only if :ref:`lds<amdgpu_synid_lds>` is omitted.
diff --git a/llvm/docs/AMDGPU/gfx10_opt.rst b/llvm/docs/AMDGPU/gfx10_opt_847aed.rst
similarity index 91%
rename from llvm/docs/AMDGPU/gfx10_opt.rst
rename to llvm/docs/AMDGPU/gfx10_opt_847aed.rst
index b4a372a02f7e2..007f643caab23 100644
--- a/llvm/docs/AMDGPU/gfx10_opt.rst
+++ b/llvm/docs/AMDGPU/gfx10_opt_847aed.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_opt:
+.. _amdgpu_synid_gfx10_opt_847aed:
opt
===
diff --git a/llvm/docs/AMDGPU/gfx10_soffset_c40a5a.rst b/llvm/docs/AMDGPU/gfx10_soffset_73dae7.rst
similarity index 72%
rename from llvm/docs/AMDGPU/gfx10_soffset_c40a5a.rst
rename to llvm/docs/AMDGPU/gfx10_soffset_73dae7.rst
index a3739bd6c6ed2..b130c8fffc2f0 100644
--- a/llvm/docs/AMDGPU/gfx10_soffset_c40a5a.rst
+++ b/llvm/docs/AMDGPU/gfx10_soffset_73dae7.rst
@@ -5,16 +5,18 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_soffset_c40a5a:
+.. _amdgpu_synid_gfx10_soffset_73dae7:
soffset
=======
-An offset added to the base address to get memory address.
+An offset from the base address.
* If offset is specified as a register, it supplies an unsigned byte offset.
* If offset is specified as a 21-bit immediate, it supplies a signed byte offset.
+Note that an *immediate* offset may be specified using either :ref:`simm21<amdgpu_synid_simm21>` operand or :ref:`offset21s<amdgpu_synid_smem_offset21s>` modifier, but not both.
+
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`simm21<amdgpu_synid_simm21>`
diff --git a/llvm/docs/AMDGPU/gfx10_soffset_59fade.rst b/llvm/docs/AMDGPU/gfx10_soffset_d01a5c.rst
similarity index 61%
rename from llvm/docs/AMDGPU/gfx10_soffset_59fade.rst
rename to llvm/docs/AMDGPU/gfx10_soffset_d01a5c.rst
index 1d5de435147e9..22ae3132cd51e 100644
--- a/llvm/docs/AMDGPU/gfx10_soffset_59fade.rst
+++ b/llvm/docs/AMDGPU/gfx10_soffset_d01a5c.rst
@@ -5,12 +5,14 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_soffset_59fade:
+.. _amdgpu_synid_gfx10_soffset_d01a5c:
soffset
=======
-An unsigned 20-bit offset added to the base address to get memory address.
+An unsigned offset from the base address. My be specified as either a register or a 20-bit immediate.
+
+Note that an *immediate* offset may be specified using either :ref:`uimm20<amdgpu_synid_uimm20>` operand or :ref:`offset20u<amdgpu_synid_smem_offset20u>` modifier, but not both.
*Size:* 1 dword.
diff --git a/llvm/docs/AMDGPU/gfx10_vdata_c61803.rst b/llvm/docs/AMDGPU/gfx10_vdata_0aba12.rst
similarity index 80%
rename from llvm/docs/AMDGPU/gfx10_vdata_c61803.rst
rename to llvm/docs/AMDGPU/gfx10_vdata_0aba12.rst
index 07401251683ff..8427034c4c888 100644
--- a/llvm/docs/AMDGPU/gfx10_vdata_c61803.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdata_0aba12.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdata_c61803:
+.. _amdgpu_synid_gfx10_vdata_0aba12:
vdata
=====
@@ -16,6 +16,6 @@ Optionally may serve as an output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
-*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vdata_b2a787.rst b/llvm/docs/AMDGPU/gfx10_vdata_16d321.rst
similarity index 80%
rename from llvm/docs/AMDGPU/gfx10_vdata_b2a787.rst
rename to llvm/docs/AMDGPU/gfx10_vdata_16d321.rst
index d0d533eeada63..c000946b93d6d 100644
--- a/llvm/docs/AMDGPU/gfx10_vdata_b2a787.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdata_16d321.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdata_b2a787:
+.. _amdgpu_synid_gfx10_vdata_16d321:
vdata
=====
@@ -16,6 +16,6 @@ Optionally may serve as an output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
-*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+*Size:* 2 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vdata_325b78.rst b/llvm/docs/AMDGPU/gfx10_vdata_35851e.rst
similarity index 81%
rename from llvm/docs/AMDGPU/gfx10_vdata_325b78.rst
rename to llvm/docs/AMDGPU/gfx10_vdata_35851e.rst
index 9f638b817e702..53036f75fdc89 100644
--- a/llvm/docs/AMDGPU/gfx10_vdata_325b78.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdata_35851e.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdata_325b78:
+.. _amdgpu_synid_gfx10_vdata_35851e:
vdata
=====
@@ -16,10 +16,10 @@ Optionally may serve as an output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
-*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>`:
* :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
-* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
Note: the surface data format is indicated in the image resource constant but not in the instruction.
diff --git a/llvm/docs/AMDGPU/gfx10_vdata_87fb90.rst b/llvm/docs/AMDGPU/gfx10_vdata_890652.rst
similarity index 80%
rename from llvm/docs/AMDGPU/gfx10_vdata_87fb90.rst
rename to llvm/docs/AMDGPU/gfx10_vdata_890652.rst
index 82d8b69960604..2e461e3ed575d 100644
--- a/llvm/docs/AMDGPU/gfx10_vdata_87fb90.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdata_890652.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdata_87fb90:
+.. _amdgpu_synid_gfx10_vdata_890652:
vdata
=====
@@ -16,6 +16,6 @@ Optionally may serve as an output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
-*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+*Size:* 4 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vdata_4d8ecf.rst b/llvm/docs/AMDGPU/gfx10_vdata_a9ff5a.rst
similarity index 81%
rename from llvm/docs/AMDGPU/gfx10_vdata_4d8ecf.rst
rename to llvm/docs/AMDGPU/gfx10_vdata_a9ff5a.rst
index 1d8719869ff3c..4c9b42728404a 100644
--- a/llvm/docs/AMDGPU/gfx10_vdata_4d8ecf.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdata_a9ff5a.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdata_4d8ecf:
+.. _amdgpu_synid_gfx10_vdata_a9ff5a:
vdata
=====
@@ -16,10 +16,10 @@ Optionally may serve as an output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
-*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>`:
* :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
-* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
Note: the surface data format is indicated in the image resource constant but not in the instruction.
diff --git a/llvm/docs/AMDGPU/gfx10_vdst_48d3a8.rst b/llvm/docs/AMDGPU/gfx10_vdst_2ea017.rst
similarity index 76%
rename from llvm/docs/AMDGPU/gfx10_vdst_48d3a8.rst
rename to llvm/docs/AMDGPU/gfx10_vdst_2ea017.rst
index 70f713fb926b3..178accdfda15d 100644
--- a/llvm/docs/AMDGPU/gfx10_vdst_48d3a8.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdst_2ea017.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdst_48d3a8:
+.. _amdgpu_synid_gfx10_vdst_2ea017:
vdst
====
@@ -14,9 +14,9 @@ Image data to load by an *image_gather4* instruction.
*Size:* 4 data elements by default. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
-:ref:`d16<amdgpu_synid_d16>` and :ref:`tfe<amdgpu_synid_tfe>` affect operand size as follows:
+:ref:`d16<amdgpu_synid_d16>` affects operand size as follows:
* :ref:`d16<amdgpu_synid_d16>` specifies that data elements in registers are packed; each value occupies 16 bits.
-* :ref:`tfe<amdgpu_synid_tfe>` adds one dword if specified.
+
*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vdst_322561.rst b/llvm/docs/AMDGPU/gfx10_vdst_322561.rst
new file mode 100644
index 0000000000000..2af4a115c4c19
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vdst_322561.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx10_vdst_322561:
+
+vdst
+====
+
+Instruction output: data read from a memory buffer.
+
+This is an optional operand. It must be used if and only if :ref:`lds<amdgpu_synid_lds>` is omitted.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vdst_5d50a1.rst b/llvm/docs/AMDGPU/gfx10_vdst_709347.rst
similarity index 76%
rename from llvm/docs/AMDGPU/gfx10_vdst_5d50a1.rst
rename to llvm/docs/AMDGPU/gfx10_vdst_709347.rst
index c24a7b0e37387..d6661c8e81708 100644
--- a/llvm/docs/AMDGPU/gfx10_vdst_5d50a1.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdst_709347.rst
@@ -5,13 +5,13 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdst_5d50a1:
+.. _amdgpu_synid_gfx10_vdst_709347:
vdst
====
Instruction output: data read from a memory buffer.
-*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vdst_719833.rst b/llvm/docs/AMDGPU/gfx10_vdst_719833.rst
deleted file mode 100644
index 2264b747b4b4b..0000000000000
--- a/llvm/docs/AMDGPU/gfx10_vdst_719833.rst
+++ /dev/null
@@ -1,21 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx10_vdst_719833:
-
-vdst
-====
-
-Instruction output: data read from a memory buffer.
-
-If :ref:`lds<amdgpu_synid_lds>` is specified, this operand is ignored by H/W and data are stored directly into LDS.
-
-*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
-
- Note that :ref:`tfe<amdgpu_synid_tfe>` and :ref:`lds<amdgpu_synid_lds>` cannot be used together.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vdst_f47754.rst b/llvm/docs/AMDGPU/gfx10_vdst_81a6ed.rst
similarity index 75%
rename from llvm/docs/AMDGPU/gfx10_vdst_f47754.rst
rename to llvm/docs/AMDGPU/gfx10_vdst_81a6ed.rst
index d80d8899af53a..2962cc520e20c 100644
--- a/llvm/docs/AMDGPU/gfx10_vdst_f47754.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdst_81a6ed.rst
@@ -5,13 +5,13 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdst_f47754:
+.. _amdgpu_synid_gfx10_vdst_81a6ed:
vdst
====
Instruction output: data read from a memory buffer.
-*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+*Size:* 3 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vdst_a49b76.rst b/llvm/docs/AMDGPU/gfx10_vdst_d71f1c.rst
similarity index 75%
rename from llvm/docs/AMDGPU/gfx10_vdst_a49b76.rst
rename to llvm/docs/AMDGPU/gfx10_vdst_d71f1c.rst
index 1a5d7028d4838..0b50699b48966 100644
--- a/llvm/docs/AMDGPU/gfx10_vdst_a49b76.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdst_d71f1c.rst
@@ -5,13 +5,13 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdst_a49b76:
+.. _amdgpu_synid_gfx10_vdst_d71f1c:
vdst
====
Instruction output: data read from a memory buffer.
-*Size:* 3 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+*Size:* 2 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vdst_d7c57e.rst b/llvm/docs/AMDGPU/gfx10_vdst_dd8a32.rst
similarity index 75%
rename from llvm/docs/AMDGPU/gfx10_vdst_d7c57e.rst
rename to llvm/docs/AMDGPU/gfx10_vdst_dd8a32.rst
index 3cecfb2000cf6..5d10df4154309 100644
--- a/llvm/docs/AMDGPU/gfx10_vdst_d7c57e.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdst_dd8a32.rst
@@ -5,13 +5,13 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdst_d7c57e:
+.. _amdgpu_synid_gfx10_vdst_dd8a32:
vdst
====
Instruction output: data read from a memory buffer.
-*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+*Size:* 4 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`
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