[PATCH] D128901: [LoongArch] Add codegen support for atomic fence, atomic load and atomic store

Mon Jul 4 00:29:02 PDT 2022

xry111 added inline comments.

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Comment at: llvm/test/CodeGen/LoongArch/ir-instruction/load-store-atomic.ll:139
+; LA64-NEXT:    dbar 0
+; LA64-NEXT:    st.d $a0, $a1, 0
+; LA64-NEXT:    jirl $zero, $ra, 0
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gonglingqin wrote:
> xry111 wrote:
> > GCC uses one instruction for this: `amswap_db.d $zero, $a1, $a0`, and to me it's correct.  Can we also use it?
> > 
> > Likewise for i32 store release operation.
> Thank you for your reminder. This may be possible. Further, we can generate different instructions according to constraints (such as instructions without fences when unordered). I'm not sure whether this optimization should be implemented in this patch or another patch. Do you have any suggestions?
Maybe in another patch, as these two instructions are not explicitly emitted by the target code, but by some "internal LLVM magic".

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D128901/new/

https://reviews.llvm.org/D128901