[llvm] 5d78768 - [RISCV] Match RISCVISD::ADD_LO in SelectAddrRegImm.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Jul 2 10:00:35 PDT 2022
Author: Craig Topper
Date: 2022-07-02T09:51:06-07:00
New Revision: 5d787689b14574fe58ba9798563f4a6df6059fbf
URL: https://github.com/llvm/llvm-project/commit/5d787689b14574fe58ba9798563f4a6df6059fbf
DIFF: https://github.com/llvm/llvm-project/commit/5d787689b14574fe58ba9798563f4a6df6059fbf.diff
LOG: [RISCV] Match RISCVISD::ADD_LO in SelectAddrRegImm.
This allows us to fold global and constant pool addresses into
load/store during isel instead of in the post-isel peephole. I
did not copy the alignment check for ConsantPoolSDNode because it
wasn't tested.
This is a step towards being able to remove the post-isel
peephole.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D128738
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index f7161e92955c..cfaafc7b53d2 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1903,10 +1903,38 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
SDLoc DL(Addr);
MVT VT = Addr.getSimpleValueType();
+ if (Addr.getOpcode() == RISCVISD::ADD_LO) {
+ Base = Addr.getOperand(0);
+ Offset = Addr.getOperand(1);
+ return true;
+ }
+
if (CurDAG->isBaseWithConstantOffset(Addr)) {
int64_t CVal = cast<ConstantSDNode>(Addr.getOperand(1))->getSExtValue();
if (isInt<12>(CVal)) {
Base = Addr.getOperand(0);
+ if (Base.getOpcode() == RISCVISD::ADD_LO) {
+ SDValue LoOperand = Base.getOperand(1);
+ if (auto *GA = dyn_cast<GlobalAddressSDNode>(LoOperand)) {
+ // If the Lo in (ADD_LO hi, lo) is a global variable's address
+ // (its low part, really), then we can rely on the alignment of that
+ // variable to provide a margin of safety before low part can overflow
+ // the 12 bits of the load/store offset. Check if CVal falls within
+ // that margin; if so (low part + CVal) can't overflow.
+ const DataLayout &DL = CurDAG->getDataLayout();
+ Align Alignment = commonAlignment(
+ GA->getGlobal()->getPointerAlignment(DL), GA->getOffset());
+ if (CVal == 0 || Alignment > CVal) {
+ int64_t CombinedOffset = CVal + GA->getOffset();
+ Base = Base.getOperand(0);
+ Offset = CurDAG->getTargetGlobalAddress(
+ GA->getGlobal(), SDLoc(LoOperand), LoOperand.getValueType(),
+ CombinedOffset, GA->getTargetFlags());
+ return true;
+ }
+ }
+ }
+
if (auto *FIN = dyn_cast<FrameIndexSDNode>(Base))
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), VT);
Offset = CurDAG->getTargetConstant(CVal, DL, VT);
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