[PATCH] D127549: RISCV: handle 64-bit PCREL data relocations
Fangrui Song via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 1 10:56:14 PDT 2022
MaskRay added a comment.
In D127549#3620985 <https://reviews.llvm.org/D127549#3620985>, @craig.topper wrote:
> In D127549#3620940 <https://reviews.llvm.org/D127549#3620940>, @craig.topper wrote:
>
>> It appears that this commit has prevented test/DebugInfo/Generic/accel-table-hash-collisions.ll from completing when the llc invocation is using a riscv triple.
>>
>> llvm-dwarfdebug prints an endless stream of
>>
>> Data 49 [
>> Atom[0]: Error extracting the value
>> ]
>> Data 50 [
>> Atom[0]: Error extracting the value
>> ]
>> Data 51 [
>> Atom[0]: Error extracting the value
>> ]
>> Data 52 [
>> Atom[0]: Error extracting the value
>> ]
>> Data 53 [
>> Atom[0]: Error extracting the value
>> ]
>>
>> with numbers that just keep increasing
>>
>> Maybe because a bunch of R_RISCV_ADD32 and R_RISCV_SUB32 relocations ends up in the .rela.apple_names section?
>
> A similar failure happens with llvm/test/DebugInfo/Generic/cross-cu-inlining.ll but for .apple_types section
I am testing adding a hack: `S.getName() == ".apple_names" || S.getName() == ".apple_types";`
I am checking why they are not metadata.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D127549/new/
https://reviews.llvm.org/D127549
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