[PATCH] D127392: [InstCombine] Combine consecutive loads which are being merged to form a wider load.

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

In D127392#3625158 <https://reviews.llvm.org/D127392#3625158>, @bipmis wrote:

> Handle some of the review comments.
> Added support for additional scenarios like reverse order loads and big-endian support.
>
> Moving the implementation to AgressiveInstCombine still open for discussion in addition with the TTI requirement.

IMO, we should move this patch to AggressiveInstCombine with conservative TTI limitations to start.

Now that we've heard from several others, I'd summarize as:

1. There's good motivation to have load combining in IR as a canonicalization.
2. But it should be limited with TTI (avoid unaligned loads, illegal operations/types).
3. Adding TTI to InstCombine is a non-starter; we don't want to have that level of target-dependence in IR canonicalization.
4. AggressiveInstCombine is lower-weight canonicalization pass that recently gained access to TTI.
5. Potential follow-ups could relax the TTI constraints and/or allow bswap formation to deal with endian diffs seen in the current tests (we do that type of transform in the backend already).


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  https://reviews.llvm.org/D127392/new/

https://reviews.llvm.org/D127392