[PATCH] D128996: [LegalizeTypes] Replace vecreduce_xor/or/and with vecreduce_add/umax/umin if not legal

[Bradley Smith via Phabricator via llvm-commits]

bsmith updated this revision to Diff 441698.
bsmith retitled this revision from "[LegalizeTypes] Replace vecreduce_xor/or with vecreduce_add/umax if not legal" to "[LegalizeTypes] Replace vecreduce_xor/or/and with vecreduce_add/umax/umin if not legal".
bsmith added a comment.

- Add support for i1 vecreduce_and -> vecreduce_umin.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128996/new/

https://reviews.llvm.org/D128996

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/reduce-and.ll
  llvm/test/CodeGen/AArch64/reduce-or.ll
  llvm/test/CodeGen/AArch64/reduce-xor.ll
  llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
  llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll

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