[PATCH] D128996: [LegalizeTypes] Replace vecreduce_xor/or with vecreduce_add/umax if not legal

[Bradley Smith via Phabricator via llvm-commits]

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This is done during type legalization since the target representation of
these nodes may not be valid until after type legalization, and after
type legalization the fact that these are dealing with i1 types may be
lost.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D128996

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/reduce-or.ll
  llvm/test/CodeGen/AArch64/reduce-xor.ll
  llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll

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