[PATCH] D127861: [AArch64][SME] Add SME addha/va intrinsics

[David Sherwood via Phabricator via llvm-commits]

david-arm marked an inline comment as done.
david-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:190-191
+def ADDVA_MPPZ_PSEUDO_S : sme_add_vector_to_tile_pseudo<ZPR32>;
+def ADDHA_MPPZ_PSEUDO_D : sme_add_vector_to_tile_pseudo<ZPR64>;
+def ADDVA_MPPZ_PSEUDO_D : sme_add_vector_to_tile_pseudo<ZPR64>;
+
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sagarkulkarni19 wrote:
> Need to enclose these instruction definitions in `let Predicates = [HasSMEI64] {..}`?
Thanks @sagarkulkarni19, that's a great spot! The real instruction definitions are guarded correctly, but the patterns and pseudos are not. I think that the mopa/mops may have a similar problem, so I'm going to look into those too.


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  https://reviews.llvm.org/D127861/new/

https://reviews.llvm.org/D127861