[llvm] 36c9e99 - [AMDGPU][GFX940][DOC][NFC] Update assembler syntax description
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 1 02:31:48 PDT 2022
Author: Dmitry Preobrazhensky
Date: 2022-07-01T12:22:57+03:00
New Revision: 36c9e9968affac543952e81637a0584a4b708597
URL: https://github.com/llvm/llvm-project/commit/36c9e9968affac543952e81637a0584a4b708597
DIFF: https://github.com/llvm/llvm-project/commit/36c9e9968affac543952e81637a0584a4b708597.diff
LOG: [AMDGPU][GFX940][DOC][NFC] Update assembler syntax description
Summary of changes:
- Update SMEM syntax (see https://reviews.llvm.org/D127314).
- Minor improvements.
Added:
llvm/docs/AMDGPU/gfx940_soffset_8a17c8.rst
llvm/docs/AMDGPU/gfx940_soffset_ba92ce.rst
Modified:
llvm/docs/AMDGPU/AMDGPUAsmGFX940.rst
Removed:
llvm/docs/AMDGPU/gfx940_soffset_7b8c50.rst
llvm/docs/AMDGPU/gfx940_soffset_f33c5c.rst
llvm/docs/AMDGPU/gfx940_vdst_08b5ba.rst
llvm/docs/AMDGPU/gfx940_vdst_0c37de.rst
llvm/docs/AMDGPU/gfx940_vdst_63b743.rst
llvm/docs/AMDGPU/gfx940_vdst_c3d63a.rst
################################################################################
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX940.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX940.rst
index a1089960d7c41..1d0f846b3ee8b 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX940.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX940.rst
@@ -6,7 +6,7 @@
**************************************************
====================================================================================
-Syntax of GFX940 Instructions
+Syntax of gfx940 Instructions
====================================================================================
.. contents::
@@ -15,7 +15,7 @@ Syntax of GFX940 Instructions
Introduction
============
-This document describes the syntax of GFX940 instructions.
+This document describes the syntax of gfx940 instructions.
Notation
========
@@ -322,14 +322,14 @@ MTBUF
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- tbuffer_load_format_d16_x :ref:`vdst<amdgpu_synid_gfx940_vdst_c3d63a>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
- tbuffer_load_format_d16_xy :ref:`vdst<amdgpu_synid_gfx940_vdst_c3d63a>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
- tbuffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid_gfx940_vdst_0c37de>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
- tbuffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid_gfx940_vdst_0c37de>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
- tbuffer_load_format_x :ref:`vdst<amdgpu_synid_gfx940_vdst_c3d63a>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
- tbuffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx940_vdst_0c37de>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
- tbuffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx940_vdst_63b743>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
- tbuffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx940_vdst_08b5ba>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ tbuffer_load_format_d16_x :ref:`vdst<amdgpu_synid_gfx940_vdst_d0c0cb>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ tbuffer_load_format_d16_xy :ref:`vdst<amdgpu_synid_gfx940_vdst_d0c0cb>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ tbuffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid_gfx940_vdst_d8236e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ tbuffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid_gfx940_vdst_d8236e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ tbuffer_load_format_x :ref:`vdst<amdgpu_synid_gfx940_vdst_d0c0cb>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ tbuffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx940_vdst_d8236e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ tbuffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx940_vdst_e2898f>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ tbuffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx940_vdst_a32035>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
tbuffer_store_format_d16_x :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
tbuffer_store_format_d16_xy :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
tbuffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
@@ -426,91 +426,91 @@ SMEM
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- s_atc_probe :ref:`probe<amdgpu_synid_gfx940_probe>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>`
- s_atc_probe_buffer :ref:`probe<amdgpu_synid_gfx940_probe>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>`
- s_atomic_add :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_add_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_and :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_and_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_cmpswap :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`b32x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_c6aec1>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`b64x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_dec :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_dec_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_inc :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_inc_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_or :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_or_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_smax :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_smax_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`i64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_smin :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_smin_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`i64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_sub :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_sub_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_swap :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_swap_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_umax :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_umax_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_umin :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_umin_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_xor :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_xor_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_add :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_add_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_and :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_and_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_cmpswap :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`b32x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_c6aec1>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`b64x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_dec :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_dec_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_inc :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_inc_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_or :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_or_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_smax :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_smax_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`i64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_smin :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_smin_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`i64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_sub :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_sub_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_swap :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_swap_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_umax :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_umax_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_umin :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_umin_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_xor :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_xor_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_load_dword :ref:`sdst<amdgpu_synid_gfx940_sdst_94342d>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx940_sdst_3bc700>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx940_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx940_sdst_362c37>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_store_dword :ref:`sdata<amdgpu_synid_gfx940_sdata_595c25>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx940_sdata_e9f591>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx940_sdata_7cbd60>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
- s_dcache_discard :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>`
- s_dcache_discard_x2 :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>`
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_atc_probe :ref:`probe<amdgpu_synid_gfx940_probe>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>`
+ s_atc_probe_buffer :ref:`probe<amdgpu_synid_gfx940_probe>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>`
+ s_atomic_add :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_add_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_and :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_and_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_cmpswap :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`b32x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_c6aec1>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`b64x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_dec :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_dec_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_inc :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_inc_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_or :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_or_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smax :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smax_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`i64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smin :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smin_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`i64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_sub :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_sub_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_swap :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_swap_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umax :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umax_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umin :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umin_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_xor :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_xor_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_add :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_add_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_and :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_and_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_cmpswap :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`b32x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_c6aec1>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`b64x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_dec :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_dec_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_inc :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_inc_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_or :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_or_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smax :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smax_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`i64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smin :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smin_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`i64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_sub :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_sub_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_swap :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_swap_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umax :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umax_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umin :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umin_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_xor :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_xor_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_load_dword :ref:`sdst<amdgpu_synid_gfx940_sdst_94342d>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx940_sdst_3bc700>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx940_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx940_sdst_362c37>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_store_dword :ref:`sdata<amdgpu_synid_gfx940_sdata_595c25>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx940_sdata_e9f591>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx940_sdata_7cbd60>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_ba92ce>` :ref:`offset20u<amdgpu_synid_smem_offset20u>` :ref:`glc<amdgpu_synid_glc>`
+ s_dcache_discard :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>`
+ s_dcache_discard_x2 :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>`
s_dcache_inv
s_dcache_inv_vol
s_dcache_wb
s_dcache_wb_vol
- s_load_dword :ref:`sdst<amdgpu_synid_gfx940_sdst_94342d>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx940_sdst_3bc700>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx940_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx940_sdst_362c37>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_load_dword :ref:`sdst<amdgpu_synid_gfx940_sdst_94342d>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx940_sdst_3bc700>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx940_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx940_sdst_362c37>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
s_memrealtime :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`::ref:`b64<amdgpu_synid_gfx940_type_deviation>`
s_memtime :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`::ref:`b64<amdgpu_synid_gfx940_type_deviation>`
- s_scratch_load_dword :ref:`sdst<amdgpu_synid_gfx940_sdst_94342d>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_0cd545>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_scratch_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_0cd545>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_scratch_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx940_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_0cd545>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_scratch_store_dword :ref:`sdata<amdgpu_synid_gfx940_sdata_595c25>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_0cd545>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_scratch_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx940_sdata_e9f591>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_0cd545>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_scratch_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx940_sdata_7cbd60>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_0cd545>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_store_dword :ref:`sdata<amdgpu_synid_gfx940_sdata_595c25>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx940_sdata_e9f591>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
- s_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx940_sdata_7cbd60>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_load_dword :ref:`sdst<amdgpu_synid_gfx940_sdst_94342d>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_0cd545>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_0cd545>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx940_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_0cd545>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_store_dword :ref:`sdata<amdgpu_synid_gfx940_sdata_595c25>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_0cd545>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx940_sdata_e9f591>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_0cd545>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx940_sdata_7cbd60>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_0cd545>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_store_dword :ref:`sdata<amdgpu_synid_gfx940_sdata_595c25>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx940_sdata_e9f591>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
+ s_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx940_sdata_7cbd60>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_8a17c8>` :ref:`offset21s<amdgpu_synid_smem_offset21s>` :ref:`glc<amdgpu_synid_glc>`
SOP1
----
@@ -2045,8 +2045,8 @@ VOPC
gfx940_simm32_a3e80c
gfx940_simm32_be0c1c
gfx940_soffset_4318ca
- gfx940_soffset_7b8c50
- gfx940_soffset_f33c5c
+ gfx940_soffset_8a17c8
+ gfx940_soffset_ba92ce
gfx940_src_4de5c6
gfx940_src_56ed80
gfx940_src_64ea89
@@ -2086,14 +2086,11 @@ VOPC
gfx940_vdata_be4895
gfx940_vdata_c8a58b
gfx940_vdata_cfb402
- gfx940_vdst_08b5ba
- gfx940_vdst_0c37de
gfx940_vdst_0f48d1
gfx940_vdst_180bef
gfx940_vdst_260aca
gfx940_vdst_5258b4
gfx940_vdst_56baf6
- gfx940_vdst_63b743
gfx940_vdst_69a144
gfx940_vdst_78dd0a
gfx940_vdst_89680f
@@ -2101,7 +2098,6 @@ VOPC
gfx940_vdst_a32035
gfx940_vdst_bce42a
gfx940_vdst_bdb32f
- gfx940_vdst_c3d63a
gfx940_vdst_c8d317
gfx940_vdst_d0c0cb
gfx940_vdst_d6f4bd
diff --git a/llvm/docs/AMDGPU/gfx940_soffset_7b8c50.rst b/llvm/docs/AMDGPU/gfx940_soffset_8a17c8.rst
similarity index 74%
rename from llvm/docs/AMDGPU/gfx940_soffset_7b8c50.rst
rename to llvm/docs/AMDGPU/gfx940_soffset_8a17c8.rst
index b76580d861b47..5ea932453b65e 100644
--- a/llvm/docs/AMDGPU/gfx940_soffset_7b8c50.rst
+++ b/llvm/docs/AMDGPU/gfx940_soffset_8a17c8.rst
@@ -5,16 +5,18 @@
* *
**************************************************
-.. _amdgpu_synid_gfx940_soffset_7b8c50:
+.. _amdgpu_synid_gfx940_soffset_8a17c8:
soffset
=======
-An offset added to the base address to get memory address.
+An offset from the base address.
* If offset is specified as a register, it supplies an unsigned byte offset.
* If offset is specified as a 21-bit immediate, it supplies a signed byte offset.
+Note that an *immediate* offset may be specified using either :ref:`simm21<amdgpu_synid_simm21>` operand or :ref:`offset21s<amdgpu_synid_smem_offset21s>` modifier, but not both.
+
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`simm21<amdgpu_synid_simm21>`
diff --git a/llvm/docs/AMDGPU/gfx940_soffset_f33c5c.rst b/llvm/docs/AMDGPU/gfx940_soffset_ba92ce.rst
similarity index 64%
rename from llvm/docs/AMDGPU/gfx940_soffset_f33c5c.rst
rename to llvm/docs/AMDGPU/gfx940_soffset_ba92ce.rst
index 9a115009db6af..710c65aa4ceed 100644
--- a/llvm/docs/AMDGPU/gfx940_soffset_f33c5c.rst
+++ b/llvm/docs/AMDGPU/gfx940_soffset_ba92ce.rst
@@ -5,12 +5,14 @@
* *
**************************************************
-.. _amdgpu_synid_gfx940_soffset_f33c5c:
+.. _amdgpu_synid_gfx940_soffset_ba92ce:
soffset
=======
-An unsigned 20-bit offset added to the base address to get memory address.
+An unsigned offset from the base address. My be specified as either a register or a 20-bit immediate.
+
+Note that an *immediate* offset may be specified using either :ref:`uimm20<amdgpu_synid_uimm20>` operand or :ref:`offset20u<amdgpu_synid_smem_offset20u>` modifier, but not both.
*Size:* 1 dword.
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_08b5ba.rst b/llvm/docs/AMDGPU/gfx940_vdst_08b5ba.rst
deleted file mode 100644
index ae0f3618795d6..0000000000000
--- a/llvm/docs/AMDGPU/gfx940_vdst_08b5ba.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx940_vdst_08b5ba:
-
-vdst
-====
-
-Instruction output: data read from a memory buffer.
-
-*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_0c37de.rst b/llvm/docs/AMDGPU/gfx940_vdst_0c37de.rst
deleted file mode 100644
index d1bdf9b86ff73..0000000000000
--- a/llvm/docs/AMDGPU/gfx940_vdst_0c37de.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx940_vdst_0c37de:
-
-vdst
-====
-
-Instruction output: data read from a memory buffer.
-
-*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_63b743.rst b/llvm/docs/AMDGPU/gfx940_vdst_63b743.rst
deleted file mode 100644
index a53055b611334..0000000000000
--- a/llvm/docs/AMDGPU/gfx940_vdst_63b743.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx940_vdst_63b743:
-
-vdst
-====
-
-Instruction output: data read from a memory buffer.
-
-*Size:* 3 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_c3d63a.rst b/llvm/docs/AMDGPU/gfx940_vdst_c3d63a.rst
deleted file mode 100644
index 7828fb14d50e6..0000000000000
--- a/llvm/docs/AMDGPU/gfx940_vdst_c3d63a.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx940_vdst_c3d63a:
-
-vdst
-====
-
-Instruction output: data read from a memory buffer.
-
-*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
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