[llvm] eec5d04 - [X86] Pre-commit tests for D128769. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-06-30T17:24:28-07:00
New Revision: eec5d04002528cf710f196b51f9f00ce37f6c7a2

URL: https://github.com/llvm/llvm-project/commit/eec5d04002528cf710f196b51f9f00ce37f6c7a2
DIFF: https://github.com/llvm/llvm-project/commit/eec5d04002528cf710f196b51f9f00ce37f6c7a2.diff

LOG: [X86] Pre-commit tests for D128769. NFC

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/shift-combine.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/shift-combine.ll b/llvm/test/CodeGen/X86/shift-combine.ll
index eddc7194f1380..c49176500cf68 100644
--- a/llvm/test/CodeGen/X86/shift-combine.ll
+++ b/llvm/test/CodeGen/X86/shift-combine.ll
@@ -418,3 +418,102 @@ then:
 if:
   unreachable
 }
+
+define i64 @ashr_add_neg_shl_i32(i64 %r) nounwind {
+; X32-LABEL: ashr_add_neg_shl_i32:
+; X32:       # %bb.0:
+; X32-NEXT:    movl $1, %eax
+; X32-NEXT:    subl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movl %eax, %edx
+; X32-NEXT:    sarl $31, %edx
+; X32-NEXT:    retl
+;
+; X64-LABEL: ashr_add_neg_shl_i32:
+; X64:       # %bb.0:
+; X64-NEXT:    shlq $32, %rdi
+; X64-NEXT:    movabsq $4294967296, %rax # imm = 0x100000000
+; X64-NEXT:    subq %rdi, %rax
+; X64-NEXT:    sarq $32, %rax
+; X64-NEXT:    retq
+  %conv = mul i64 %r, -4294967296
+  %sext = add i64 %conv, 4294967296
+  %conv1 = ashr i64 %sext, 32
+  ret i64 %conv1
+}
+
+define i64 @ashr_add_neg_shl_i8(i64 %r) nounwind {
+; X32-LABEL: ashr_add_neg_shl_i8:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    shll $24, %eax
+; X32-NEXT:    movl $33554432, %edx # imm = 0x2000000
+; X32-NEXT:    subl %eax, %edx
+; X32-NEXT:    movl %edx, %eax
+; X32-NEXT:    sarl $24, %eax
+; X32-NEXT:    sarl $31, %edx
+; X32-NEXT:    retl
+;
+; X64-LABEL: ashr_add_neg_shl_i8:
+; X64:       # %bb.0:
+; X64-NEXT:    shlq $56, %rdi
+; X64-NEXT:    movabsq $144115188075855872, %rax # imm = 0x200000000000000
+; X64-NEXT:    subq %rdi, %rax
+; X64-NEXT:    sarq $56, %rax
+; X64-NEXT:    retq
+  %conv = mul i64 %r, -72057594037927936
+  %sext = add i64 %conv, 144115188075855872
+  %conv1 = ashr i64 %sext, 56
+  ret i64 %conv1
+}
+
+define <4 x i32> @ashr_add_neg_shl_v4i8(<4 x i32> %r) nounwind {
+; X32-LABEL: ashr_add_neg_shl_v4i8:
+; X32:       # %bb.0:
+; X32-NEXT:    pushl %ebp
+; X32-NEXT:    pushl %ebx
+; X32-NEXT:    pushl %edi
+; X32-NEXT:    pushl %esi
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %ebp
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %ebx
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; X32-NEXT:    shll $24, %edx
+; X32-NEXT:    shll $24, %esi
+; X32-NEXT:    shll $24, %ebx
+; X32-NEXT:    shll $24, %ebp
+; X32-NEXT:    movl $16777216, %ecx # imm = 0x1000000
+; X32-NEXT:    movl $16777216, %edi # imm = 0x1000000
+; X32-NEXT:    subl %ebp, %edi
+; X32-NEXT:    movl $16777216, %ebp # imm = 0x1000000
+; X32-NEXT:    subl %ebx, %ebp
+; X32-NEXT:    movl $16777216, %ebx # imm = 0x1000000
+; X32-NEXT:    subl %esi, %ebx
+; X32-NEXT:    subl %edx, %ecx
+; X32-NEXT:    sarl $24, %ecx
+; X32-NEXT:    sarl $24, %ebx
+; X32-NEXT:    sarl $24, %ebp
+; X32-NEXT:    sarl $24, %edi
+; X32-NEXT:    movl %edi, 12(%eax)
+; X32-NEXT:    movl %ebp, 8(%eax)
+; X32-NEXT:    movl %ebx, 4(%eax)
+; X32-NEXT:    movl %ecx, (%eax)
+; X32-NEXT:    popl %esi
+; X32-NEXT:    popl %edi
+; X32-NEXT:    popl %ebx
+; X32-NEXT:    popl %ebp
+; X32-NEXT:    retl $4
+;
+; X64-LABEL: ashr_add_neg_shl_v4i8:
+; X64:       # %bb.0:
+; X64-NEXT:    pslld $24, %xmm0
+; X64-NEXT:    movdqa {{.*#+}} xmm1 = [16777216,16777216,16777216,16777216]
+; X64-NEXT:    psubd %xmm0, %xmm1
+; X64-NEXT:    psrad $24, %xmm1
+; X64-NEXT:    movdqa %xmm1, %xmm0
+; X64-NEXT:    retq
+  %conv = mul <4 x i32> %r, <i32 -16777216, i32 -16777216, i32 -16777216, i32 -16777216>
+  %sext = add <4 x i32> %conv, <i32 16777216, i32 16777216, i32 16777216, i32 16777216>
+  %conv1 = ashr <4 x i32> %sext, <i32 24, i32 24, i32 24, i32 24>
+  ret <4 x i32> %conv1
+}