[PATCH] D128769: [DAGCombiner][X86] Fold sra (sub AddC, (shl X, N1C)), N1C --> sext (sub AddC1',(trunc X to (width - N1C)))

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:9294
+  if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB) &&
+      N0.hasOneUse() && N1C) {
+    bool IsAdd = N0.getOpcode() == ISD::ADD;
----------------
Move N1C earlier? Move the expensive hasOneUse as late as possible


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:9300
+      if (ConstantSDNode *AddC =
+              isConstOrConstSplat(N0.getOperand(IsAdd ? 1 : 0))) {
+        // Determine what the truncate's type would be and ask the target if
----------------
Does this have to be a splat? I think technically only N1C has to be and AddC can be non-uniform except it requires the ShiftC calculation to be refactored for general constant folding. But I'm not certain how often isTruncateFree is going to return true for vector types....


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D128769/new/

https://reviews.llvm.org/D128769