[llvm] ab2e1c0 - [AArch64] Make FeatureFuseAdrpAdd a tune feature

[Fangrui Song via llvm-commits]

Author: Fangrui Song
Date: 2022-06-30T10:32:38-07:00
New Revision: ab2e1c0804f86501e8548756f8a3deb41870db44

URL: https://github.com/llvm/llvm-project/commit/ab2e1c0804f86501e8548756f8a3deb41870db44
DIFF: https://github.com/llvm/llvm-project/commit/ab2e1c0804f86501e8548756f8a3deb41870db44.diff

LOG: [AArch64] Make FeatureFuseAdrpAdd a tune feature

Update D120104 to add FeatureFuseAdrpAdd to Processor#TuneFeatures
instead of Processor#Features, similar to FeatureFuseAES, and matching
Tune*.

This enables FeatureFuseAdrpAdd for `clang -mcpu=xxx -mtune=generic` even
if xxx does not set FeatureFuseAdrpAdd.

Reviewed By: alexander-shaposhnikov, peter.smith

Differential Revision: https://reviews.llvm.org/D128787

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64.td
    llvm/test/CodeGen/AArch64/misched-fusion-lit.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 42542611b4ab..f053b4533b03 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -1090,14 +1090,14 @@ def ProcessorFeatures {
   // ETE and TRBE are future architecture extensions. We temporarily enable them
   // by default for users targeting generic AArch64. The extensions do not
   // affect code generated by the compiler and can be used only by explicitly
-  // mentioning the new system register names in assembly. FeatureFuseAdrpAdd is
-  // enabled under Generic to allow linker merging optimizations.
-  list<SubtargetFeature> Generic = [FeatureFPARMv8, FeatureNEON, FeatureETE,
-                                    FeatureFuseAdrpAdd];
+  // mentioning the new system register names in assembly.
+  list<SubtargetFeature> Generic = [FeatureFPARMv8, FeatureNEON, FeatureETE];
 }
 
+// FeatureFuseAdrpAdd is enabled under Generic to allow linker merging
+// optimizations.
 def : ProcessorModel<"generic", CortexA55Model, ProcessorFeatures.Generic,
-                     [FeatureFuseAES, FeaturePostRAScheduler]>;
+                     [FeatureFuseAES, FeatureFuseAdrpAdd, FeaturePostRAScheduler]>;
 def : ProcessorModel<"cortex-a35", CortexA53Model, ProcessorFeatures.A53,
                      [TuneA35]>;
 def : ProcessorModel<"cortex-a34", CortexA53Model, ProcessorFeatures.A53,

diff  --git a/llvm/test/CodeGen/AArch64/misched-fusion-lit.ll b/llvm/test/CodeGen/AArch64/misched-fusion-lit.ll
index bc70e9fe7c9f..7dc123f81e31 100644
--- a/llvm/test/CodeGen/AArch64/misched-fusion-lit.ll
+++ b/llvm/test/CodeGen/AArch64/misched-fusion-lit.ll
@@ -22,6 +22,19 @@ entry:
 ; CHECKFUSE-NEXT: add {{x[0-9]+}}, [[R]], :lo12:litp
 }
 
+define dso_local i8* @litp_tune_generic(i32 %a, i32 %b) "tune-cpu"="generic" {
+entry:
+  %add = add nsw i32 %b, %a
+  %idx.ext = sext i32 %add to i64
+  %add.ptr = getelementptr i8, i8* bitcast (i8* (i32, i32)* @litp_tune_generic to i8*), i64 %idx.ext
+  store i8* %add.ptr, i8** @g, align 8
+  ret i8* %add.ptr
+
+; CHECK-LABEL: litp_tune_generic:
+; CHECK:         adrp [[R:x[0-9]+]], litp_tune_generic
+; CHECK-NEXT:    add {{x[0-9]+}}, [[R]], :lo12:litp_tune_generic
+}
+
 define dso_local i32 @liti(i32 %a, i32 %b) {
 entry:
   %add = add i32 %a, -262095121