[PATCH] D128665: [AArch64] Make nxv1i1 types a legal type for SVE.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

Sorry for the incremental review.  This was not intentional, just how my code review time worked out for this patch.



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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:6664-6667
+  unsigned InNumElts = InVT.getVectorMinNumElements();
+  unsigned WidenNumElts = NVT.getVectorMinNumElements();
   if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
     unsigned NumConcat = WidenNumElts / InNumElts;
----------------
A few weeks back I extended TypeSize.h to include methods that allow us to handle such cases without resorting to `getVectorMinNumElements()`. See `hasKnownScalarFactor` and `getKnownScalarFactor`. The `>` code can use `NVT.bitsGT(InVT)`.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:10484
+  if (VT == MVT::nxv1i1)
+    return getPUNPKLO(DAG, DL,
+                      DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::nxv2i1, ID,
----------------
Rather than using `PUNPKLO` directly can you use `ISD::EXTRACT_SUBVECTOR`?


Repository:
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https://reviews.llvm.org/D128665