[PATCH] D128917: [SCEVExpander] Use IRBuilder to create BinOp

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

Unfortunately, I do think the LSR changes are problematic.  I suspect this may break assumptions in LSR about register liveness in hard to predict ways.  e.g. LoopStrengthReduce/X86/pr46943.ll undoes an optimization to reduce live ranges.  (Though, why that particular example wasn't killed by RLEV I have no idea.)

You could make this conditional on LSRMode.  You could have two builders, one simplifying and one not.  Note sure if that's worth your while or not though.


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  https://reviews.llvm.org/D128917/new/

https://reviews.llvm.org/D128917