[PATCH] D128756: [AMDGPU] gfx11 WMMA instruction support

[Piotr Sobczak via Phabricator via llvm-commits]

piotr added a comment.





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Comment at: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp:3739-3740
+    MachineOperand &Root) const {
+  assert((Root.isImm() && (Root.getImm() == -1 || Root.getImm() == 0)) &&
+         "expected i1 value");
+  unsigned Mods = SISrcMods::OP_SEL_1;
----------------
arsenm wrote:
> Joe_Nash wrote:
> > arsenm wrote:
> > > Probably should have a verifier check this, or just rely on 0/non-0
> > I don't know what to do here. The intrinsic has an i1 field. If you put a non-i1 value that will be reported right? Given that, we are asserting that other parts of ISel haven't transformed this value incorrectly. Also, we do the same thing in selectDotIUVOP3PMods, line 3726. Please let me know what could be done.
> I'd just invert the check below to != 0. The machine verifier is certainly not enforcing this be 0/-1 for booleans. Practically speaking, this would only come up for hand written MIR
> I don't know what to do here. The intrinsic has an i1 field. If you put a non-i1 value that will be reported right? Given that, we are asserting that other parts of ISel haven't transformed this value incorrectly. Also, we do the same thing in selectDotIUVOP3PMods, line 3726. Please let me know what could be done.

Indeed, this was strongly inspired by the existing code in selectDotIUVOP3PMods, which handles the intrinsic in a similar way.


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https://reviews.llvm.org/D128756