[PATCH] D128839: [DirectX backend] Add createHandle BufferLoad/Store DXIL operation

[Xiang Li via Phabricator via llvm-commits]

python3kgae added inline comments.


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Comment at: llvm/include/llvm/IR/IntrinsicsDXIL.td:22
+
+def int_dxil_buffer_load : Intrinsic<[ llvm_any_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty ],
+ [ llvm_i64_ty, llvm_i32_ty, llvm_i32_ty], [IntrReadMem, IntrWillReturn]>;
----------------
beanz wrote:
> python3kgae wrote:
> > beanz wrote:
> > > Do you have a plan for taking LLVM load instructions and converting them to these intrinsics?
> > > 
> > > I think we need to think about how we want to translate LLVM gep/load/store instructions into DXIL ops, and I don't think we should add these intrinsics until we know what that is going to look like.
> > These intrinsics are trying to make the distance from hlsl to DXIL shorter.
> > They're just wrapper for DXIL operation functions so generate DXIL is easier.
> > 
> >  I did experiment to generate DXIL directly from GEP/load/store, then found create intrinsic might help the translation.
> I still don't know that these are the _right_ intrinsics. How are we going to map GEP/load/store to these intrinsics?
It will not be a simple map, we'll need a pass to translate GEP/load/store to these intrinsics.
These intrinsics are to make the pass easier to write and leave the details like DXIL opcode, DXIL struct type to DXILOpLowering pass.

Maybe we can allow GEP/load/store in final DXIL for future DXIL version, but to generate early version of DXIL, these intrinsics will be 
 helpful.


Repository:
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  https://reviews.llvm.org/D128839/new/

https://reviews.llvm.org/D128839