[PATCH] D128902: [AArch64][SVE] Create AArch64ISD node for DUPQLANE

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm accepted this revision.
paulwalker-arm added a comment.
This revision is now accepted and ready to land.

A potential code placement improvement but otherwise looks good.



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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:675-690
+  def : Pat<(nxv16i8 (AArch64duplane128 nxv16i8:$Op1, i64:$imm)),
+            (nxv16i8 (DUP_ZZI_Q $Op1, $imm))>;
+  def : Pat<(nxv8i16 (AArch64duplane128 nxv8i16:$Op1, i64:$imm)),
+            (nxv8i16 (DUP_ZZI_Q $Op1, $imm))>;
+  def : Pat<(nxv4i32 (AArch64duplane128 nxv4i32:$Op1, i64:$imm)),
+            (nxv4i32 (DUP_ZZI_Q $Op1, $imm))>;
+  def : Pat<(nxv2i64 (AArch64duplane128 nxv2i64:$Op1, i64:$imm)),
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Sorry I didn't have access to code or would have suggested this before but I think these can be moved into the multiclass that defines sve_int_perm_dup_i.  I can see it already has patterns for the B,H,S and D forms.


Repository:
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  https://reviews.llvm.org/D128902/new/

https://reviews.llvm.org/D128902