[PATCH] D127549: RISCV: handle 64-bit PCREL data relocations

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

It appears that this commit has prevented test/DebugInfo/Generic/accel-table-hash-collisions.ll from completing when the llc invocation is using a riscv triple.

llvm-dwarfdebug prints an endless stream of

  Data 49 [                                                                  
    Atom[0]: Error extracting the value                                      
  ]                                                                          
  Data 50 [                                                                  
    Atom[0]: Error extracting the value                                      
  ]                                                                          
  Data 51 [                                                                  
    Atom[0]: Error extracting the value                                      
  ]                                                                          
  Data 52 [                                                                  
    Atom[0]: Error extracting the value                                      
  ]                                                                          
  Data 53 [                                                                  
    Atom[0]: Error extracting the value                                      
  ]

with numbers that just keep increasing


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D127549/new/

https://reviews.llvm.org/D127549