[PATCH] D128869: [RISCV] Fold (sra (add (shl X, 32), C1), 32 - C) -> (shl (sext_inreg (add X, C1), C)

[Craig Topper via Phabricator via llvm-commits]

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Similar for a subtract with a constant left hand side.

(sra (add (shl X, 32), C1 <https://reviews.llvm.org/C1><<32), 32) is the canonical IR from InstCombine
for (sext (add (trunc X to i32), 32) to i32).

For RISCV, we should lower this as addiw which means turning it into
(sext_inreg (add X, C1 <https://reviews.llvm.org/C1>)).

There is an existing DAG combine to convert back to (sext (add (trunc X
to i32), 32) to i32), but it requires isTruncateFree to return true
and for i32 to be a legal type as it used sign_extend and truncate
nodes. So that doesn't work for RISCV.

If the outer sra happens be used by a shl by constant, it will be
folded and the shift amount of the sra will be changed before we
can do our own DAG combine. This requires us to match the more
general pattern and restore the shl.

I had wanted to do this as a separate (add (shl X, 32), C1 <https://reviews.llvm.org/C1><<32) ->
(shl (add X, C1 <https://reviews.llvm.org/C1>), 32) combine, but that hit an infinite loop for some
values of C1 <https://reviews.llvm.org/C1>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D128869

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll

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