[llvm] 75095e6 - [RISCV] Pre-commit tests for D128843. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-06-29T12:12:42-07:00
New Revision: 75095e628124b88138fe2f9eb9d603fd352cafbc

URL: https://github.com/llvm/llvm-project/commit/75095e628124b88138fe2f9eb9d603fd352cafbc
DIFF: https://github.com/llvm/llvm-project/commit/75095e628124b88138fe2f9eb9d603fd352cafbc.diff

LOG: [RISCV] Pre-commit tests for D128843. NFC

Added: 
    llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll b/llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll
new file mode 100644
index 000000000000..f52f4eef4f53
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll
@@ -0,0 +1,84 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64I
+
+; Test that we turn (sra (shl X, 32), 32-C) into (slli (sext.w X), C)
+
+define i64 @test1(i64 %a) nounwind {
+; RV64I-LABEL: test1:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    srai a0, a0, 30
+; RV64I-NEXT:    ret
+  %1 = shl i64 %a, 32
+  %2 = ashr i64 %1, 30
+  ret i64 %2
+}
+
+define i64 @test2(i32 signext %a) nounwind {
+; RV64I-LABEL: test2:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    srai a0, a0, 29
+; RV64I-NEXT:    ret
+  %1 = zext i32 %a to i64
+  %2 = shl i64 %1, 32
+  %3 = ashr i64 %2, 29
+  ret i64 %3
+}
+
+define i64 @test3(i32* %a) nounwind {
+; RV64I-LABEL: test3:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lw a0, 0(a0)
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    srai a0, a0, 28
+; RV64I-NEXT:    ret
+  %1 = load i32, i32* %a
+  %2 = zext i32 %1 to i64
+  %3 = shl i64 %2, 32
+  %4 = ashr i64 %3, 28
+  ret i64 %4
+}
+
+define i64 @test4(i32 signext %a, i32 signext %b) nounwind {
+; RV64I-LABEL: test4:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addw a0, a0, a1
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    srai a0, a0, 2
+; RV64I-NEXT:    ret
+  %1 = add i32 %a, %b
+  %2 = zext i32 %1 to i64
+  %3 = shl i64 %2, 32
+  %4 = ashr i64 %3, 2
+  ret i64 %4
+}
+
+define i64 @test5(i32 signext %a, i32 signext %b) nounwind {
+; RV64I-LABEL: test5:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    srai a0, a0, 1
+; RV64I-NEXT:    ret
+  %1 = xor i32 %a, %b
+  %2 = zext i32 %1 to i64
+  %3 = shl i64 %2, 32
+  %4 = ashr i64 %3, 1
+  ret i64 %4
+}
+
+define i64 @test6(i32 signext %a, i32 signext %b) nounwind {
+; RV64I-LABEL: test6:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    sllw a0, a0, a1
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    srai a0, a0, 16
+; RV64I-NEXT:    ret
+  %1 = shl i32 %a, %b
+  %2 = zext i32 %1 to i64
+  %3 = shl i64 %2, 32
+  %4 = ashr i64 %3, 16
+  ret i64 %4
+}