[PATCH] D128843: [RISCV] DAG combine (sra (shl X, 32), 32 - C) -> (sra (sext_inreg X, i32), C).

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

I think you need to push the commit with rv64i-shift-sext?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D128843/new/

https://reviews.llvm.org/D128843