[llvm] dd48d3a - Revert "[RISCV] Avoid changing etype for splat of 0 or -1"
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 29 10:27:19 PDT 2022
Author: Philip Reames
Date: 2022-06-29T10:27:02-07:00
New Revision: dd48d3ad0e5fff78e6e3a7fd8ca830624ccb8e33
URL: https://github.com/llvm/llvm-project/commit/dd48d3ad0e5fff78e6e3a7fd8ca830624ccb8e33
DIFF: https://github.com/llvm/llvm-project/commit/dd48d3ad0e5fff78e6e3a7fd8ca830624ccb8e33.diff
LOG: Revert "[RISCV] Avoid changing etype for splat of 0 or -1"
This reverts commit 755c84c62cda80b0acf51ccc5653fc6d64536f7e. A bug was reported on the original review thread (https://reviews.llvm.org/D128006), and on inspection this patch is simply wrong. It needs to be checking for VLInBytes, not MaxVL. These happen to be the same when using AVL=VLMAX (which is quite common), but this does not fold when AVL != VLMAX.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index c7c9f909d35d0..fc0a983f65426 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -82,38 +82,6 @@ static bool isScalarMoveInstr(const MachineInstr &MI) {
}
}
-static bool isSplatMoveInstr(const MachineInstr &MI) {
- switch (MI.getOpcode()) {
- default:
- return false;
- case RISCV::PseudoVMV_V_X_M1:
- case RISCV::PseudoVMV_V_X_M2:
- case RISCV::PseudoVMV_V_X_M4:
- case RISCV::PseudoVMV_V_X_M8:
- case RISCV::PseudoVMV_V_X_MF2:
- case RISCV::PseudoVMV_V_X_MF4:
- case RISCV::PseudoVMV_V_X_MF8:
- case RISCV::PseudoVMV_V_I_M1:
- case RISCV::PseudoVMV_V_I_M2:
- case RISCV::PseudoVMV_V_I_M4:
- case RISCV::PseudoVMV_V_I_M8:
- case RISCV::PseudoVMV_V_I_MF2:
- case RISCV::PseudoVMV_V_I_MF4:
- case RISCV::PseudoVMV_V_I_MF8:
- return true;
- }
-}
-
-static bool isSplatOfZeroOrMinusOne(const MachineInstr &MI) {
- if (!isSplatMoveInstr(MI))
- return false;
-
- const MachineOperand &SrcMO = MI.getOperand(1);
- if (SrcMO.isImm())
- return SrcMO.getImm() == 0 || SrcMO.getImm() == -1;
- return SrcMO.isReg() && SrcMO.getReg() == RISCV::X0;
-}
-
/// Get the EEW for a load or store instruction. Return None if MI is not
/// a load or store which ignores SEW.
static Optional<unsigned> getEEWForLoadStore(const MachineInstr &MI) {
@@ -421,14 +389,6 @@ static DemandedFields getDemanded(const MachineInstr &MI) {
Res.MaskPolicy = false;
}
- // A splat of 0/-1 is always a splat of 0/-1, regardless of etype.
- // TODO: We're currently demanding VL + SEWLMULRatio which is sufficient
- // but not neccessary. What we really need is VLInBytes.
- if (isSplatOfZeroOrMinusOne(MI)) {
- Res.SEW = false;
- Res.LMUL = false;
- }
-
// If this is a mask reg operation, it only cares about VLMAX.
// TODO: Possible extensions to this logic
// * Probably ok if available VLMax is larger than demanded
diff --git a/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll b/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
index 574283fd96c19..1fae357540b7e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
@@ -27,9 +27,11 @@ define void @constant_folding_crash(i8* %v54, <4 x <4 x i32>*> %lanes.a, <4 x <4
; RV32-NEXT: vmsne.vi v0, v11, 0
; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV32-NEXT: vmerge.vvm v8, v9, v8, v0
+; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; RV32-NEXT: vmv.v.i v9, 0
+; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV32-NEXT: vmv.x.s a0, v8
-; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
+; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; RV32-NEXT: vmv1r.v v0, v10
; RV32-NEXT: vmerge.vim v8, v9, 1, v0
; RV32-NEXT: vmv.x.s a1, v8
@@ -52,9 +54,11 @@ define void @constant_folding_crash(i8* %v54, <4 x <4 x i32>*> %lanes.a, <4 x <4
; RV64-NEXT: vmsne.vi v0, v13, 0
; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; RV64-NEXT: vmerge.vvm v8, v10, v8, v0
+; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; RV64-NEXT: vmv.v.i v10, 0
+; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; RV64-NEXT: vmv.x.s a0, v8
-; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
+; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; RV64-NEXT: vmv1r.v v0, v12
; RV64-NEXT: vmerge.vim v8, v10, 1, v0
; RV64-NEXT: vmv.x.s a1, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
index 1626ebb1084be..59226a81e060d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
@@ -1567,7 +1567,7 @@ define <4 x i1> @pass_vector_mask_arg_via_stack(<4 x i1> %v) {
; LMULMAX1-NEXT: .cfi_offset ra, -8
; LMULMAX1-NEXT: li a0, 8
; LMULMAX1-NEXT: sd a0, 128(sp)
-; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
+; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: vse32.v v8, (sp)
; LMULMAX1-NEXT: addi a0, sp, 112
@@ -1584,6 +1584,7 @@ define <4 x i1> @pass_vector_mask_arg_via_stack(<4 x i1> %v) {
; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: addi a0, sp, 16
; LMULMAX1-NEXT: vse32.v v8, (a0)
+; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vmerge.vim v9, v9, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
index edb582513ce83..dd2a5a7ade935 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
@@ -41,8 +41,8 @@ define void @fcmp_une_vv_v4f32(<4 x float>* %x, <4 x float>* %y, <4 x i1>* %z) {
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vle32.v v9, (a1)
; CHECK-NEXT: vmfne.vv v0, v8, v9
-; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
@@ -66,8 +66,8 @@ define void @fcmp_une_vv_v4f32_nonans(<4 x float>* %x, <4 x float>* %y, <4 x i1>
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vle32.v v9, (a1)
; CHECK-NEXT: vmfne.vv v0, v8, v9
-; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
@@ -91,8 +91,8 @@ define void @fcmp_ogt_vv_v2f64(<2 x double>* %x, <2 x double>* %y, <2 x i1>* %z)
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vle64.v v9, (a1)
; CHECK-NEXT: vmflt.vv v0, v9, v8
-; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
@@ -116,8 +116,8 @@ define void @fcmp_ogt_vv_v2f64_nonans(<2 x double>* %x, <2 x double>* %y, <2 x i
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vle64.v v9, (a1)
; CHECK-NEXT: vmflt.vv v0, v9, v8
-; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
@@ -205,8 +205,8 @@ define void @fcmp_ole_vv_v4f64(<4 x double>* %x, <4 x double>* %y, <4 x i1>* %z)
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vle64.v v10, (a1)
; CHECK-NEXT: vmfle.vv v0, v8, v10
-; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
@@ -230,8 +230,8 @@ define void @fcmp_ole_vv_v4f64_nonans(<4 x double>* %x, <4 x double>* %y, <4 x i
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vle64.v v10, (a1)
; CHECK-NEXT: vmfle.vv v0, v8, v10
-; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
@@ -463,8 +463,8 @@ define void @fcmp_ord_vv_v4f16(<4 x half>* %x, <4 x half>* %y, <4 x i1>* %z) {
; CHECK-NEXT: vmfeq.vv v8, v8, v8
; CHECK-NEXT: vmfeq.vv v9, v9, v9
; CHECK-NEXT: vmand.mm v0, v9, v8
-; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
@@ -490,8 +490,8 @@ define void @fcmp_uno_vv_v4f16(<2 x half>* %x, <2 x half>* %y, <2 x i1>* %z) {
; CHECK-NEXT: vmfne.vv v8, v8, v8
; CHECK-NEXT: vmfne.vv v9, v9, v9
; CHECK-NEXT: vmor.mm v0, v9, v8
-; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
@@ -546,8 +546,8 @@ define void @fcmp_une_vf_v4f32(<4 x float>* %x, float %y, <4 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
@@ -571,8 +571,8 @@ define void @fcmp_une_vf_v4f32_nonans(<4 x float>* %x, float %y, <4 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
@@ -596,8 +596,8 @@ define void @fcmp_ogt_vf_v2f64(<2 x double>* %x, double %y, <2 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
@@ -621,8 +621,8 @@ define void @fcmp_ogt_vf_v2f64_nonans(<2 x double>* %x, double %y, <2 x i1>* %z)
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
@@ -710,8 +710,8 @@ define void @fcmp_ole_vf_v4f64(<4 x double>* %x, double %y, <4 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
@@ -735,8 +735,8 @@ define void @fcmp_ole_vf_v4f64_nonans(<4 x double>* %x, double %y, <4 x i1>* %z)
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
@@ -969,8 +969,8 @@ define void @fcmp_ord_vf_v4f16(<4 x half>* %x, half %y, <4 x i1>* %z) {
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v8, v8, v8
; CHECK-NEXT: vmand.mm v0, v8, v9
-; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
@@ -997,8 +997,8 @@ define void @fcmp_uno_vf_v4f16(<2 x half>* %x, half %y, <2 x i1>* %z) {
; CHECK-NEXT: vmfne.vf v9, v9, fa0
; CHECK-NEXT: vmfne.vv v8, v8, v8
; CHECK-NEXT: vmor.mm v0, v8, v9
-; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
@@ -1054,8 +1054,8 @@ define void @fcmp_une_fv_v4f32(<4 x float>* %x, float %y, <4 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
@@ -1079,8 +1079,8 @@ define void @fcmp_une_fv_v4f32_nonans(<4 x float>* %x, float %y, <4 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
@@ -1104,8 +1104,8 @@ define void @fcmp_ogt_fv_v2f64(<2 x double>* %x, double %y, <2 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
@@ -1129,8 +1129,8 @@ define void @fcmp_ogt_fv_v2f64_nonans(<2 x double>* %x, double %y, <2 x i1>* %z)
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
@@ -1218,8 +1218,8 @@ define void @fcmp_ole_fv_v4f64(<4 x double>* %x, double %y, <4 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
@@ -1243,8 +1243,8 @@ define void @fcmp_ole_fv_v4f64_nonans(<4 x double>* %x, double %y, <4 x i1>* %z)
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
@@ -1477,8 +1477,8 @@ define void @fcmp_ord_fv_v4f16(<4 x half>* %x, half %y, <4 x i1>* %z) {
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v8, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v8
-; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
@@ -1505,8 +1505,8 @@ define void @fcmp_uno_fv_v4f16(<2 x half>* %x, half %y, <2 x i1>* %z) {
; CHECK-NEXT: vmfne.vf v9, v9, fa0
; CHECK-NEXT: vmfne.vv v8, v8, v8
; CHECK-NEXT: vmor.mm v0, v9, v8
-; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
index b6c022de6fca8..5eff5f224740a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
@@ -154,8 +154,8 @@ define <8 x i1> @fp2si_v8f32_v8i1(<8 x float> %x) {
; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v10, v9
; LMULMAX1-NEXT: vand.vi v9, v10, 1
; LMULMAX1-NEXT: vmsne.vi v0, v9, 0
-; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
+; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vmerge.vim v9, v9, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
@@ -188,8 +188,8 @@ define <8 x i1> @fp2ui_v8f32_v8i1(<8 x float> %x) {
; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v10, v9
; LMULMAX1-NEXT: vand.vi v9, v10, 1
; LMULMAX1-NEXT: vmsne.vi v0, v9, 0
-; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
+; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vmerge.vim v9, v9, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
@@ -564,8 +564,8 @@ define <8 x i1> @fp2si_v8f64_v8i1(<8 x double> %x) {
; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v13, v9
; LMULMAX1-NEXT: vand.vi v9, v13, 1
; LMULMAX1-NEXT: vmsne.vi v0, v9, 0
-; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
+; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vmerge.vim v13, v9, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v13, 2
@@ -620,8 +620,8 @@ define <8 x i1> @fp2ui_v8f64_v8i1(<8 x double> %x) {
; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v13, v9
; LMULMAX1-NEXT: vand.vi v9, v13, 1
; LMULMAX1-NEXT: vmsne.vi v0, v9, 0
-; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
+; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vmerge.vim v13, v9, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v13, 2
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