[PATCH] D128584: [X86][AMX] Split greedy RA for tile register

Wed Jun 29 02:30:12 PDT 2022

LuoYuanke added a comment.

In D128584#3618128 <https://reviews.llvm.org/D128584#3618128>, @LuoYuanke wrote:

> In D128584#3618012 <https://reviews.llvm.org/D128584#3618012>, @nikic wrote:
>
>> It looks like this change had some compile-time impact: http://llvm-compile-time-tracker.com/compare.php?from=fc2d96c334a15d00965eb57a99d49e46728641db&to=5cb09798700aecff1f9f61b7cd80852c61e10fa8&stat=instructions I wonder whether there is any easy way to avoid the overhead if tile registers are not used?
>
> We check the ShouldAllocateClass() in RegAllocBase::enqueue(). The overhead looks small because in the first GreedyRA pass most vritual register is not enqueued yet, but it seems I was wrong. I notice the regession is in O3 <https://reviews.llvm.org/owners/package/3/> build, let me check if any more passes are added unexpectedly in O3 <https://reviews.llvm.org/owners/package/3/>

Let me check ShouldAllocateClass() earlier to see if it can fix the regression.

Repository:
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https://reviews.llvm.org/D128584