[llvm] 2fcc495 - [AArch64] Update test case.

[Guozhi Wei via llvm-commits]

Author: Guozhi Wei
Date: 2022-06-29T01:37:56Z
New Revision: 2fcc495549e11d587cd22bf02fabfcfa1a764562

URL: https://github.com/llvm/llvm-project/commit/2fcc495549e11d587cd22bf02fabfcfa1a764562
DIFF: https://github.com/llvm/llvm-project/commit/2fcc495549e11d587cd22bf02fabfcfa1a764562.diff

LOG: [AArch64] Update test case.

Replace the new generated virtual register number with a macro to avoid
name mismatch due to different configuration of compiler.

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/machine-combiner-subadd2.mir

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/machine-combiner-subadd2.mir b/llvm/test/CodeGen/AArch64/machine-combiner-subadd2.mir
index 395fa3f023e1..d1770bb25fae 100644
--- a/llvm/test/CodeGen/AArch64/machine-combiner-subadd2.mir
+++ b/llvm/test/CodeGen/AArch64/machine-combiner-subadd2.mir
@@ -8,8 +8,8 @@
 # 32 bit.
 
 # CHECK-LABEL: name: test1
-# CHECK:       %10:gpr32common = SUBWrr killed %3, %4
-# CHECK-NEXT:  %7:gpr32 = SUBWrr killed %10, %5
+# CHECK:       [[TMP:%[0-9]+]]:gpr32common = SUBWrr killed %3, %4
+# CHECK-NEXT:  %7:gpr32 = SUBWrr killed [[TMP]], %5
 
 name:            test1
 registers:
@@ -41,8 +41,8 @@ body:              |
 # 64 bit.
 
 # CHECK-LABEL: name: test2
-# CHECK:       %10:gpr64common = SUBXrr killed %3, %4
-# CHECK-NEXT:  %7:gpr64 = SUBXrr killed %10, %5
+# CHECK:       [[TMP:%[0-9]+]]:gpr64common = SUBXrr killed %3, %4
+# CHECK-NEXT:  %7:gpr64 = SUBXrr killed [[TMP]], %5
 
 name:            test2
 registers:
@@ -107,8 +107,8 @@ body:              |
 # Dead define of flag registers should not block transformation.
 
 # CHECK-LABEL: name: test4
-# CHECK:       %10:gpr64common = SUBXrr killed %3, %4
-# CHECK-NEXT:  %7:gpr64 = SUBXrr killed %10, %5
+# CHECK:       [[TMP:%[0-9]+]]:gpr64common = SUBXrr killed %3, %4
+# CHECK-NEXT:  %7:gpr64 = SUBXrr killed [[TMP]], %5
 
 name:            test4
 registers: