[llvm] 5dcc525 - [RISCV] Fold (add X, [-4096, -2049]) or (add X, [2048,4096]) into load/store address during isel.

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Tue Jun 28 17:00:54 PDT 2022


Author: Craig Topper
Date: 2022-06-28T16:59:39-07:00
New Revision: 5dcc5254925ad84b3949b2bef8345579611bd6f9

URL: https://github.com/llvm/llvm-project/commit/5dcc5254925ad84b3949b2bef8345579611bd6f9
DIFF: https://github.com/llvm/llvm-project/commit/5dcc5254925ad84b3949b2bef8345579611bd6f9.diff

LOG: [RISCV] Fold (add X, [-4096, -2049]) or (add X, [2048,4096]) into load/store address during isel.

Previously we iseled this to a pair of ADDIs and relied on a post
isel peephole to fold one of the ADDIs into the load/store. Now
we split the immediate in two parts the same way isel does and fold
one of the pieces. If the add has a non-memory use it will emit
two isels and larger one will CSE with the ADDI we created for the
the memory use.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D128741

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 5152a1e2def9..3c3412e82a17 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1852,6 +1852,26 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
     }
   }
 
+  // Handle ADD with large immediates.
+  if (Addr.getOpcode() == ISD::ADD && isa<ConstantSDNode>(Addr.getOperand(1))) {
+    int64_t CVal = cast<ConstantSDNode>(Addr.getOperand(1))->getSExtValue();
+    assert(!isInt<12>(CVal) && "simm12 not already handled?");
+
+    if (isInt<12>(CVal / 2) && isInt<12>(CVal - CVal / 2)) {
+      // We can use an ADDI for part of the offset and fold the rest into the
+      // load/store. This mirrors the AddiPair PatFrag in RISCVInstrInfo.td.
+      int64_t Adj = CVal < 0 ? -2048 : 2047;
+      SDLoc DL(Addr);
+      MVT VT = Addr.getSimpleValueType();
+      Base = SDValue(
+          CurDAG->getMachineNode(RISCV::ADDI, DL, VT, Addr.getOperand(0),
+                                 CurDAG->getTargetConstant(Adj, DL, VT)),
+          0);
+      Offset = CurDAG->getTargetConstant(CVal - Adj, DL, VT);
+      return true;
+    }
+  }
+
   Base = Addr;
   Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Subtarget->getXLenVT());
   return true;


        


More information about the llvm-commits mailing list