[llvm] 21895c6 - [AMDGPU] Relax verification of soffset in scalar stores

Stanislav Mekhanoshin via llvm-commits llvm-commits at lists.llvm.org
Tue Jun 28 16:10:17 PDT 2022


Author: Stanislav Mekhanoshin
Date: 2022-06-28T16:10:08-07:00
New Revision: 21895c6b5060d71aa4bbe619cfc3baeb1df1894b

URL: https://github.com/llvm/llvm-project/commit/21895c6b5060d71aa4bbe619cfc3baeb1df1894b
DIFF: https://github.com/llvm/llvm-project/commit/21895c6b5060d71aa4bbe619cfc3baeb1df1894b.diff

LOG: [AMDGPU] Relax verification of soffset in scalar stores

It must use m0 only on GFX8. Later chips can use ang SGPR.

Differential Revision: https://reviews.llvm.org/D128765

Added: 
    llvm/test/CodeGen/AMDGPU/verify-scalar-store.mir

Modified: 
    llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 61f37d80b1a61..5b5555d5dca87 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4439,7 +4439,8 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
   }
 
   if (isSMRD(MI)) {
-    if (MI.mayStore()) {
+    if (MI.mayStore() &&
+        ST.getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS) {
       // The register offset form of scalar stores may only use m0 as the
       // soffset register.
       const MachineOperand *Soff = getNamedOperand(MI, AMDGPU::OpName::soffset);

diff  --git a/llvm/test/CodeGen/AMDGPU/verify-scalar-store.mir b/llvm/test/CodeGen/AMDGPU/verify-scalar-store.mir
new file mode 100644
index 0000000000000..eabc273bd17b4
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/verify-scalar-store.mir
@@ -0,0 +1,13 @@
+# RUN: not --crash llc -march=amdgcn -mcpu=tonga -run-pass=machineverifier -o /dev/null %s 2>&1 | FileCheck -check-prefix=GFX8-ERR %s
+# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=machineverifier -o - %s 2>&1 | FileCheck -check-prefix=GFX9 %s
+
+# GFX8-ERR: *** Bad machine code: scalar stores must use m0 as offset register ***
+# GFX9: S_STORE_DWORD_SGPR
+---
+name:            scalar_store_soffset_sgpr
+body:             |
+  bb.0:
+    S_STORE_DWORD_SGPR undef $sgpr2, undef $sgpr0_sgpr1, undef $sgpr10, 0
+    S_ENDPGM 0
+
+...


        


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