[PATCH] D127516: RegisterCoalescer: Fix verifier error when merging copy of undef

Matt Arsenault via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Jun 28 15:33:35 PDT 2022


arsenm added inline comments.


================
Comment at: llvm/test/CodeGen/AMDGPU/undef-subreg-use-after-coalesce.mir:35-36
     ; CHECK-NEXT: dead %0.sub1:vreg_128 = V_MOV_B32_e32 0, implicit $exec
-    ; CHECK-NEXT: S_ENDPGM 0, implicit undef %2.sub1:vreg_64
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
+    ; CHECK-NEXT: S_ENDPGM 0, implicit [[DEF]].sub1
     undef %0.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
----------------
arsenm wrote:
> MatzeB wrote:
> > This isn't a case of a live-out value though? Shouldn't it continue to use an `undef` flag over an `IMPLICIT_DEF`?
> This is the minor regression I mentioned
On second inspection, I think this is arguably better. %0.sub1 is dead in the original MIR. Previously, the use on the S_ENDPGM was made undead by the coalescing. The implicit_def keeps %0.sub1 dead and defs a separate register for the undef use


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  https://reviews.llvm.org/D127516/new/

https://reviews.llvm.org/D127516



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