[PATCH] D124192: [AMDGPU] Callee must always spill writelane VGPRs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm accepted this revision.
arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:1273
+  for (MachineBasicBlock &MBB : MF) {
+    for (auto &Reg : MFI->getWWMVGPRs())
+      MBB.addLiveIn(Reg.first);
----------------
cdevadas wrote:
> arsenm wrote:
> > Were WWM registers not reserved? I thought they were
> Yes, they are. See `SIRegisterInfo::getReservedRegs`, I added some comments below. 
I think we ought to either use the live in strategy or mark as reserved, but not both. Should clean this up in a later patch


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  https://reviews.llvm.org/D124192/new/

https://reviews.llvm.org/D124192