[llvm] f1cfaa9 - [AMDGPU] Use GFX11 S_PACK_HL instruction in more cases
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 28 06:39:50 PDT 2022
Author: Joe Nash
Date: 2022-06-28T14:35:19+01:00
New Revision: f1cfaa956def453c2df086ce38665a2669246e5d
URL: https://github.com/llvm/llvm-project/commit/f1cfaa956def453c2df086ce38665a2669246e5d
DIFF: https://github.com/llvm/llvm-project/commit/f1cfaa956def453c2df086ce38665a2669246e5d.diff
LOG: [AMDGPU] Use GFX11 S_PACK_HL instruction in more cases
Differential Revision: https://reviews.llvm.org/D128527
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstructions.td
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
llvm/test/CodeGen/AMDGPU/build_vector.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 08c10610f0064..4e6e2d0c69d33 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -665,6 +665,8 @@ bool AMDGPUInstructionSelector::selectG_BUILD_VECTOR_TRUNC(
//
// (build_vector_trunc (lshr_oneuse $src0, 16), (lshr_oneuse $src1, 16)
// => (S_PACK_HH_B32_B16 $src0, $src1)
+ // (build_vector_trunc (lshr_oneuse SReg_32:$src0, 16), $src1)
+ // => (S_PACK_HL_B32_B16 $src0, $src1)
// (build_vector_trunc $src0, (lshr_oneuse SReg_32:$src1, 16))
// => (S_PACK_LH_B32_B16 $src0, $src1)
// (build_vector_trunc $src0, $src1)
@@ -684,14 +686,20 @@ bool AMDGPUInstructionSelector::selectG_BUILD_VECTOR_TRUNC(
} else if (Shift1) {
Opc = AMDGPU::S_PACK_LH_B32_B16;
MI.getOperand(2).setReg(ShiftSrc1);
- } else if (Shift0 && ConstSrc1 && ConstSrc1->Value == 0) {
- // build_vector_trunc (lshr $src0, 16), 0 -> s_lshr_b32 $src0, 16
- auto MIB = BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_LSHR_B32), Dst)
- .addReg(ShiftSrc0)
- .addImm(16);
+ } else if (Shift0) {
+ if (ConstSrc1 && ConstSrc1->Value == 0) {
+ // build_vector_trunc (lshr $src0, 16), 0 -> s_lshr_b32 $src0, 16
+ auto MIB = BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_LSHR_B32), Dst)
+ .addReg(ShiftSrc0)
+ .addImm(16);
- MI.eraseFromParent();
- return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
+ MI.eraseFromParent();
+ return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
+ }
+ if (STI.hasSPackHL()) {
+ Opc = AMDGPU::S_PACK_HL_B32_B16;
+ MI.getOperand(1).setReg(ShiftSrc0);
+ }
}
MI.setDesc(TII.get(Opc));
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index d8cfd509e5173..61f37d80b1a61 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -6173,6 +6173,7 @@ MachineBasicBlock *SIInstrInfo::moveToVALU(MachineInstr &TopInst,
case AMDGPU::S_PACK_LL_B32_B16:
case AMDGPU::S_PACK_LH_B32_B16:
+ case AMDGPU::S_PACK_HL_B32_B16:
case AMDGPU::S_PACK_HH_B32_B16:
movePackToVALU(Worklist, MRI, Inst);
Inst.eraseFromParent();
@@ -7086,6 +7087,17 @@ void SIInstrInfo::movePackToVALU(SetVectorType &Worklist,
.add(Src1);
break;
}
+ case AMDGPU::S_PACK_HL_B32_B16: {
+ Register TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+ BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHRREV_B32_e64), TmpReg)
+ .addImm(16)
+ .add(Src0);
+ BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHL_OR_B32_e64), ResultReg)
+ .add(Src1)
+ .addImm(16)
+ .addReg(TmpReg, RegState::Kill);
+ break;
+ }
case AMDGPU::S_PACK_HH_B32_B16: {
Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
Register TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index e39763a5ebe00..12abd5ffddf10 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2699,6 +2699,15 @@ def : GCNPat <
>;
} // End SubtargetPredicate = HasVOP3PInsts
+// With multiple uses of the shift, this will duplicate the shift and
+// increase register pressure.
+let SubtargetPredicate = isGFX11Plus in
+def : GCNPat <
+ (v2i16 (build_vector (i16 (trunc (srl_oneuse SReg_32:$src0, (i32 16)))), (i16 SReg_32:$src1))),
+ (v2i16 (S_PACK_HL_B32_B16 SReg_32:$src0, SReg_32:$src1))
+>;
+
+
def : GCNPat <
(v2f16 (scalar_to_vector f16:$src0)),
(COPY $src0)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir
index 1da2d9695f2dc..0af2d08ab9ce8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GFX9PLUS,GFX9 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GFX9PLUS,GFX11 %s
---
name: test_build_vector_trunc_s_v2s16_s_s32_s_s32
@@ -11,13 +12,13 @@ body: |
bb.0:
liveins: $sgpr0, $sgpr1
- ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_s_s32
- ; GFX9: liveins: $sgpr0, $sgpr1
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
- ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[COPY1]]
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_s_s32
+ ; GFX9PLUS: liveins: $sgpr0, $sgpr1
+ ; GFX9PLUS-NEXT: {{ $}}
+ ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[COPY1]]
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
@@ -34,13 +35,13 @@ body: |
bb.0:
liveins: $sgpr0, $sgpr1
- ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_lh
- ; GFX9: liveins: $sgpr0, $sgpr1
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
- ; GFX9-NEXT: [[S_PACK_LH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LH_B32_B16 [[COPY]], [[COPY1]]
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LH_B32_B16_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_pack_lh
+ ; GFX9PLUS: liveins: $sgpr0, $sgpr1
+ ; GFX9PLUS-NEXT: {{ $}}
+ ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX9PLUS-NEXT: [[S_PACK_LH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LH_B32_B16 [[COPY]], [[COPY1]]
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LH_B32_B16_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = G_CONSTANT i32 16
@@ -49,9 +50,9 @@ body: |
S_ENDPGM 0, implicit %4
...
-# There is no s_pack_hl_b32
+# s_pack_hl_b32 was introduced in GFX11
---
-name: test_build_vector_trunc_s_pack_lh_swapped
+name: test_build_vector_trunc_s_pack_hl
legalized: true
regBankSelected: true
tracksRegLiveness: true
@@ -60,7 +61,7 @@ body: |
bb.0:
liveins: $sgpr0, $sgpr1
- ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_lh_swapped
+ ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_hl
; GFX9: liveins: $sgpr0, $sgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
@@ -69,6 +70,13 @@ body: |
; GFX9-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_LSHR_B32_]], [[COPY]]
; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+ ; GFX11-LABEL: name: test_build_vector_trunc_s_pack_hl
+ ; GFX11: liveins: $sgpr0, $sgpr1
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX11-NEXT: [[S_PACK_HL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_HL_B32_B16 [[COPY1]], [[COPY]]
+ ; GFX11-NEXT: S_ENDPGM 0, implicit [[S_PACK_HL_B32_B16_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = G_CONSTANT i32 16
@@ -87,13 +95,13 @@ body: |
bb.0:
liveins: $sgpr0, $sgpr1
- ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_hh
- ; GFX9: liveins: $sgpr0, $sgpr1
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
- ; GFX9-NEXT: [[S_PACK_HH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_HH_B32_B16 [[COPY]], [[COPY1]]
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_HH_B32_B16_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_pack_hh
+ ; GFX9PLUS: liveins: $sgpr0, $sgpr1
+ ; GFX9PLUS-NEXT: {{ $}}
+ ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX9PLUS-NEXT: [[S_PACK_HH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_HH_B32_B16 [[COPY]], [[COPY1]]
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_HH_B32_B16_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = G_CONSTANT i32 16
@@ -114,13 +122,13 @@ body: |
bb.0:
liveins: $sgpr0
- ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_s_0_s32
- ; GFX9: liveins: $sgpr0
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
- ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]]
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_s_0_s32
+ ; GFX9PLUS: liveins: $sgpr0
+ ; GFX9PLUS-NEXT: {{ $}}
+ ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+ ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]]
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = G_CONSTANT i32 0
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
@@ -137,13 +145,13 @@ body: |
bb.0:
liveins: $sgpr0
- ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_0_s32_s_s32
- ; GFX9: liveins: $sgpr0
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
- ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]]
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_0_s32_s_s32
+ ; GFX9PLUS: liveins: $sgpr0
+ ; GFX9PLUS-NEXT: {{ $}}
+ ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+ ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]]
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = G_CONSTANT i32 0
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %1, %0
@@ -160,11 +168,11 @@ body: |
bb.0:
liveins: $sgpr0
- ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_s_undef_s32
- ; GFX9: liveins: $sgpr0
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[COPY]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_s_undef_s32
+ ; GFX9PLUS: liveins: $sgpr0
+ ; GFX9PLUS-NEXT: {{ $}}
+ ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[COPY]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = G_IMPLICIT_DEF
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
@@ -181,13 +189,13 @@ body: |
bb.0:
liveins: $sgpr0
- ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_undef_s32_s_s32
- ; GFX9: liveins: $sgpr0
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GFX9-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
- ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[COPY]]
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_undef_s32_s_s32
+ ; GFX9PLUS: liveins: $sgpr0
+ ; GFX9PLUS-NEXT: {{ $}}
+ ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9PLUS-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[COPY]]
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = G_IMPLICIT_DEF
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %1, %0
@@ -204,13 +212,13 @@ body: |
bb.0:
liveins: $sgpr1
- ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_undef_s_s32
- ; GFX9: liveins: $sgpr1
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr1
- ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[COPY]]
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_undef_s_s32
+ ; GFX9PLUS: liveins: $sgpr1
+ ; GFX9PLUS-NEXT: {{ $}}
+ ; GFX9PLUS-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[COPY]]
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
%0:sgpr(s32) = G_IMPLICIT_DEF
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
@@ -227,11 +235,11 @@ body: |
bb.0:
liveins: $sgpr0
- ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_undef
- ; GFX9: liveins: $sgpr0
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[COPY]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_undef
+ ; GFX9PLUS: liveins: $sgpr0
+ ; GFX9PLUS-NEXT: {{ $}}
+ ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[COPY]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = G_IMPLICIT_DEF
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
@@ -248,13 +256,13 @@ body: |
bb.0:
liveins: $sgpr1
- ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_zero_s_s32
- ; GFX9: liveins: $sgpr1
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr1
- ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]]
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_zero_s_s32
+ ; GFX9PLUS: liveins: $sgpr1
+ ; GFX9PLUS-NEXT: {{ $}}
+ ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+ ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]]
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
%0:sgpr(s32) = G_CONSTANT i32 0
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
@@ -271,13 +279,13 @@ body: |
bb.0:
liveins: $sgpr0
- ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_zero
- ; GFX9: liveins: $sgpr0
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
- ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]]
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_zero
+ ; GFX9PLUS: liveins: $sgpr0
+ ; GFX9PLUS-NEXT: {{ $}}
+ ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+ ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]]
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = G_CONSTANT i32 0
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
@@ -294,12 +302,12 @@ body: |
bb.0:
liveins: $sgpr0
- ; GFX9-LABEL: name: test_build_vector_trunc_lshr16_zero
- ; GFX9: liveins: $sgpr0
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GFX9-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], 16, implicit-def $scc
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_LSHR_B32_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_lshr16_zero
+ ; GFX9PLUS: liveins: $sgpr0
+ ; GFX9PLUS-NEXT: {{ $}}
+ ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9PLUS-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], 16, implicit-def $scc
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_LSHR_B32_]]
%0:sgpr(s32) = G_CONSTANT i32 0
%1:sgpr(s32) = COPY $sgpr0
%2:sgpr(s32) = G_CONSTANT i32 16
@@ -319,15 +327,15 @@ body: |
bb.0:
liveins: $sgpr0, $sgpr1
- ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_lh_multi_use
- ; GFX9: liveins: $sgpr0, $sgpr1
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
- ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
- ; GFX9-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
- ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_LSHR_B32_]]
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]], implicit [[S_LSHR_B32_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_pack_lh_multi_use
+ ; GFX9PLUS: liveins: $sgpr0, $sgpr1
+ ; GFX9PLUS-NEXT: {{ $}}
+ ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
+ ; GFX9PLUS-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
+ ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_LSHR_B32_]]
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]], implicit [[S_LSHR_B32_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = G_CONSTANT i32 16
@@ -346,15 +354,15 @@ body: |
bb.0:
liveins: $sgpr0, $sgpr1
- ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_hh_multi_use_lhs
- ; GFX9: liveins: $sgpr0, $sgpr1
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
- ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
- ; GFX9-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
- ; GFX9-NEXT: [[S_PACK_LH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LH_B32_B16 [[S_LSHR_B32_]], [[COPY1]]
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LH_B32_B16_]], implicit [[S_LSHR_B32_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_pack_hh_multi_use_lhs
+ ; GFX9PLUS: liveins: $sgpr0, $sgpr1
+ ; GFX9PLUS-NEXT: {{ $}}
+ ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
+ ; GFX9PLUS-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+ ; GFX9PLUS-NEXT: [[S_PACK_LH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LH_B32_B16 [[S_LSHR_B32_]], [[COPY1]]
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LH_B32_B16_]], implicit [[S_LSHR_B32_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = G_CONSTANT i32 16
@@ -384,6 +392,15 @@ body: |
; GFX9-NEXT: [[S_LSHR_B32_1:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_LSHR_B32_]], [[S_LSHR_B32_1]]
; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]], implicit [[S_LSHR_B32_1]]
+ ; GFX11-LABEL: name: test_build_vector_trunc_s_pack_hh_multi_use_rhs
+ ; GFX11: liveins: $sgpr0, $sgpr1
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
+ ; GFX11-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
+ ; GFX11-NEXT: [[S_PACK_HL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_HL_B32_B16 [[COPY]], [[S_LSHR_B32_]]
+ ; GFX11-NEXT: S_ENDPGM 0, implicit [[S_PACK_HL_B32_B16_]], implicit [[S_LSHR_B32_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = G_CONSTANT i32 16
@@ -403,15 +420,15 @@ body: |
bb.0:
liveins: $sgpr0, $sgpr1
- ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_lh_wrong_shift_amt
- ; GFX9: liveins: $sgpr0, $sgpr1
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
- ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 15
- ; GFX9-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
- ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_LSHR_B32_]]
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_pack_lh_wrong_shift_amt
+ ; GFX9PLUS: liveins: $sgpr0, $sgpr1
+ ; GFX9PLUS-NEXT: {{ $}}
+ ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 15
+ ; GFX9PLUS-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
+ ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_LSHR_B32_]]
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = G_CONSTANT i32 15
@@ -430,16 +447,16 @@ body: |
bb.0:
liveins: $sgpr0, $sgpr1
- ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_hh_wrong_shift_amt
- ; GFX9: liveins: $sgpr0, $sgpr1
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
- ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 15
- ; GFX9-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
- ; GFX9-NEXT: [[S_LSHR_B32_1:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
- ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_LSHR_B32_]], [[S_LSHR_B32_1]]
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_pack_hh_wrong_shift_amt
+ ; GFX9PLUS: liveins: $sgpr0, $sgpr1
+ ; GFX9PLUS-NEXT: {{ $}}
+ ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 15
+ ; GFX9PLUS-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+ ; GFX9PLUS-NEXT: [[S_LSHR_B32_1:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
+ ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_LSHR_B32_]], [[S_LSHR_B32_1]]
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = G_CONSTANT i32 15
@@ -458,9 +475,9 @@ tracksRegLiveness: true
body: |
bb.0:
- ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_constant_constant
- ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 29884539
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_constant_constant
+ ; GFX9PLUS: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 29884539
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]]
%0:sgpr(s32) = G_CONSTANT i32 123
%1:sgpr(s32) = G_CONSTANT i32 456
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
@@ -476,9 +493,9 @@ tracksRegLiveness: true
body: |
bb.0:
- ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_constant_impdef
- ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_constant_impdef
+ ; GFX9PLUS: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]]
%0:sgpr(s32) = G_CONSTANT i32 123
%1:sgpr(s32) = G_IMPLICIT_DEF
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
@@ -494,11 +511,11 @@ tracksRegLiveness: true
body: |
bb.0:
- ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_impdef_constant
- ; GFX9: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
- ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123
- ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[S_MOV_B32_]]
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_impdef_constant
+ ; GFX9PLUS: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123
+ ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[S_MOV_B32_]]
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
%0:sgpr(s32) = G_IMPLICIT_DEF
%1:sgpr(s32) = G_CONSTANT i32 123
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
@@ -514,9 +531,9 @@ tracksRegLiveness: true
body: |
bb.0:
- ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_impdef_impdef
- ; GFX9: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[DEF]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_impdef_impdef
+ ; GFX9PLUS: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[DEF]]
%0:sgpr(s32) = G_IMPLICIT_DEF
%1:sgpr(s32) = G_IMPLICIT_DEF
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
@@ -532,9 +549,9 @@ tracksRegLiveness: true
body: |
bb.0:
- ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_zext_constant_zext_constant
- ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 29884539
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_zext_constant_zext_constant
+ ; GFX9PLUS: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 29884539
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]]
%0:sgpr(s16) = G_CONSTANT i16 123
%1:sgpr(s16) = G_CONSTANT i16 456
%2:sgpr(s32) = G_ZEXT %0
@@ -552,13 +569,13 @@ tracksRegLiveness: true
body: |
bb.0:
- ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_zext_impdef_zext_constant
- ; GFX9: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
- ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123
- ; GFX9-NEXT: [[S_BFE_U32_:%[0-9]+]]:sreg_32 = S_BFE_U32 [[DEF]], 1048576, implicit-def $scc
- ; GFX9-NEXT: [[S_BFE_U32_1:%[0-9]+]]:sreg_32 = S_BFE_U32 [[S_MOV_B32_]], 1048576, implicit-def $scc
- ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_BFE_U32_]], [[S_BFE_U32_1]]
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_zext_impdef_zext_constant
+ ; GFX9PLUS: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123
+ ; GFX9PLUS-NEXT: [[S_BFE_U32_:%[0-9]+]]:sreg_32 = S_BFE_U32 [[DEF]], 1048576, implicit-def $scc
+ ; GFX9PLUS-NEXT: [[S_BFE_U32_1:%[0-9]+]]:sreg_32 = S_BFE_U32 [[S_MOV_B32_]], 1048576, implicit-def $scc
+ ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_BFE_U32_]], [[S_BFE_U32_1]]
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
%0:sgpr(s16) = G_IMPLICIT_DEF
%1:sgpr(s16) = G_CONSTANT i16 123
%2:sgpr(s32) = G_ZEXT %0
@@ -576,9 +593,9 @@ tracksRegLiveness: true
body: |
bb.0:
- ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_sext_constant_sext_constant
- ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294836208
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_sext_constant_sext_constant
+ ; GFX9PLUS: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294836208
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]]
%0:sgpr(s16) = G_CONSTANT i16 -16
%1:sgpr(s16) = G_CONSTANT i16 -3
%2:sgpr(s32) = G_SEXT %0
@@ -596,9 +613,9 @@ tracksRegLiveness: true
body: |
bb.0:
- ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_anyext_constant_anyext_constant
- ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 29884539
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_anyext_constant_anyext_constant
+ ; GFX9PLUS: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 29884539
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]]
%0:sgpr(s16) = G_CONSTANT i16 123
%1:sgpr(s16) = G_CONSTANT i16 456
%2:sgpr(s32) = G_ANYEXT %0
@@ -616,11 +633,11 @@ tracksRegLiveness: true
body: |
bb.0:
- ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_anyext_impdef_anyext_constant
- ; GFX9: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
- ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123
- ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[S_MOV_B32_]]
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_anyext_impdef_anyext_constant
+ ; GFX9PLUS: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123
+ ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[S_MOV_B32_]]
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
%0:sgpr(s16) = G_IMPLICIT_DEF
%1:sgpr(s16) = G_CONSTANT i16 123
%2:sgpr(s32) = G_ANYEXT %0
@@ -639,13 +656,13 @@ body: |
bb.0:
liveins: $sgpr0
- ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_var_constant
- ; GFX9: liveins: $sgpr0
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 456
- ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]]
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_var_constant
+ ; GFX9PLUS: liveins: $sgpr0
+ ; GFX9PLUS-NEXT: {{ $}}
+ ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 456
+ ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]]
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = G_CONSTANT i32 456
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
@@ -662,13 +679,13 @@ body: |
bb.0:
liveins: $sgpr0
- ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_constant_var
- ; GFX9: liveins: $sgpr0
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 456
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]]
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_constant_var
+ ; GFX9PLUS: liveins: $sgpr0
+ ; GFX9PLUS-NEXT: {{ $}}
+ ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 456
+ ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]]
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
%0:sgpr(s32) = G_CONSTANT i32 456
%1:sgpr(s32) = COPY $sgpr0
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
@@ -685,13 +702,13 @@ body: |
bb.0:
liveins: $sgpr0
- ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_var_0
- ; GFX9: liveins: $sgpr0
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
- ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]]
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_var_0
+ ; GFX9PLUS: liveins: $sgpr0
+ ; GFX9PLUS-NEXT: {{ $}}
+ ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+ ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]]
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = G_CONSTANT i32 0
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
@@ -708,13 +725,13 @@ body: |
bb.0:
liveins: $sgpr0
- ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_0_var
- ; GFX9: liveins: $sgpr0
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]]
- ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
+ ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_0_var
+ ; GFX9PLUS: liveins: $sgpr0
+ ; GFX9PLUS-NEXT: {{ $}}
+ ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+ ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]]
+ ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
%0:sgpr(s32) = G_CONSTANT i32 0
%1:sgpr(s32) = COPY $sgpr0
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
index d51228d25c721..2b1fef8972317 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
@@ -2,7 +2,8 @@
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -o - %s | FileCheck -check-prefix=GFX6 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s | FileCheck -check-prefix=GFX8 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
define i7 @v_saddsat_i7(i7 %lhs, i7 %rhs) {
; GFX6-LABEL: v_saddsat_i7:
@@ -44,15 +45,15 @@ define i7 @v_saddsat_i7(i7 %lhs, i7 %rhs) {
; GFX9-NEXT: v_ashrrev_i16_e32 v0, 9, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_saddsat_i7:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_lshlrev_b16 v0, 9, v0
-; GFX10-NEXT: v_lshlrev_b16 v1, 9, v1
-; GFX10-NEXT: v_add_nc_i16 v0, v0, v1 clamp
-; GFX10-NEXT: v_ashrrev_i16 v0, 9, v0
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_i7:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_lshlrev_b16 v0, 9, v0
+; GFX10PLUS-NEXT: v_lshlrev_b16 v1, 9, v1
+; GFX10PLUS-NEXT: v_add_nc_i16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT: v_ashrrev_i16 v0, 9, v0
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call i7 @llvm.sadd.sat.i7(i7 %lhs, i7 %rhs)
ret i7 %result
}
@@ -105,15 +106,15 @@ define amdgpu_ps i7 @s_saddsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_saddsat_i7:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_bfe_u32 s2, 9, 0x100000
-; GFX10-NEXT: s_lshl_b32 s0, s0, s2
-; GFX10-NEXT: s_lshl_b32 s1, s1, s2
-; GFX10-NEXT: v_add_nc_i16 v0, s0, s1 clamp
-; GFX10-NEXT: v_ashrrev_i16 v0, 9, v0
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_i7:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_bfe_u32 s2, 9, 0x100000
+; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, s2
+; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, s2
+; GFX10PLUS-NEXT: v_add_nc_i16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT: v_ashrrev_i16 v0, 9, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i7 @llvm.sadd.sat.i7(i7 %lhs, i7 %rhs)
ret i7 %result
}
@@ -158,15 +159,15 @@ define i8 @v_saddsat_i8(i8 %lhs, i8 %rhs) {
; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_saddsat_i8:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_lshlrev_b16 v0, 8, v0
-; GFX10-NEXT: v_lshlrev_b16 v1, 8, v1
-; GFX10-NEXT: v_add_nc_i16 v0, v0, v1 clamp
-; GFX10-NEXT: v_ashrrev_i16 v0, 8, v0
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_i8:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_lshlrev_b16 v0, 8, v0
+; GFX10PLUS-NEXT: v_lshlrev_b16 v1, 8, v1
+; GFX10PLUS-NEXT: v_add_nc_i16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT: v_ashrrev_i16 v0, 8, v0
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call i8 @llvm.sadd.sat.i8(i8 %lhs, i8 %rhs)
ret i8 %result
}
@@ -219,15 +220,15 @@ define amdgpu_ps i8 @s_saddsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_saddsat_i8:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_bfe_u32 s2, 8, 0x100000
-; GFX10-NEXT: s_lshl_b32 s0, s0, s2
-; GFX10-NEXT: s_lshl_b32 s1, s1, s2
-; GFX10-NEXT: v_add_nc_i16 v0, s0, s1 clamp
-; GFX10-NEXT: v_ashrrev_i16 v0, 8, v0
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_i8:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_bfe_u32 s2, 8, 0x100000
+; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, s2
+; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, s2
+; GFX10PLUS-NEXT: v_add_nc_i16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT: v_ashrrev_i16 v0, 8, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i8 @llvm.sadd.sat.i8(i8 %lhs, i8 %rhs)
ret i8 %result
}
@@ -329,6 +330,27 @@ define i16 @v_saddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX10-NEXT: v_and_b32_sdwa v1, v0, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_saddsat_v2i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_lshrrev_b32_e32 v2, 8, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT: v_and_or_b32 v0, 0xffff, v0, v2
+; GFX11-NEXT: v_and_or_b32 v1, 0xffff, v1, v3
+; GFX11-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_i16 v0, v0, v1 clamp
+; GFX11-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8>
%result = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
@@ -455,6 +477,30 @@ define amdgpu_ps i16 @s_saddsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_saddsat_v2i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshr_b32 s2, s0, 8
+; GFX11-NEXT: s_lshr_b32 s3, s1, 8
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s2
+; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s3
+; GFX11-NEXT: s_lshr_b32 s2, s0, 16
+; GFX11-NEXT: s_lshr_b32 s3, s1, 16
+; GFX11-NEXT: s_lshl_b32 s0, s0, 0x80008
+; GFX11-NEXT: s_lshl_b32 s2, s2, 8
+; GFX11-NEXT: s_lshl_b32 s1, s1, 0x80008
+; GFX11-NEXT: s_lshl_b32 s3, s3, 8
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s2
+; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s3
+; GFX11-NEXT: v_pk_add_i16 v0, s0, s1 clamp
+; GFX11-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: ; return to shader part epilog
%lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8>
%result = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
@@ -653,6 +699,42 @@ define i32 @v_saddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX10-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_saddsat_v4i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_lshrrev_b32_e32 v2, 8, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v5, 24, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v6, 24, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-NEXT: v_and_or_b32 v0, 0xffff, v0, v2
+; GFX11-NEXT: v_and_or_b32 v1, 0xffff, v1, v3
+; GFX11-NEXT: v_and_or_b32 v2, 0xffff, v4, v5
+; GFX11-NEXT: v_and_or_b32 v3, 0xffff, v7, v6
+; GFX11-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_i16 v0, v0, v1 clamp
+; GFX11-NEXT: v_pk_add_i16 v1, v2, v3 clamp
+; GFX11-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_ashrrev_i16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT: v_bfe_u32 v2, v0, 16, 8
+; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v1
+; GFX11-NEXT: v_bfe_u32 v1, v1, 16, 8
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; GFX11-NEXT: v_and_or_b32 v0, v0, 0xff, v2
+; GFX11-NEXT: v_or3_b32 v0, v0, v3, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8>
%result = call <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
@@ -895,6 +977,47 @@ define amdgpu_ps i32 @s_saddsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) {
; GFX10-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_saddsat_v4i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshr_b32 s2, s0, 8
+; GFX11-NEXT: s_lshr_b32 s4, s1, 8
+; GFX11-NEXT: s_pack_ll_b32_b16 s2, s0, s2
+; GFX11-NEXT: s_pack_ll_b32_b16 s4, s1, s4
+; GFX11-NEXT: s_lshr_b32 s6, s2, 16
+; GFX11-NEXT: s_lshl_b32 s2, s2, 0x80008
+; GFX11-NEXT: s_lshl_b32 s6, s6, 8
+; GFX11-NEXT: s_lshr_b32 s3, s0, 24
+; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s6
+; GFX11-NEXT: s_lshr_b32 s6, s4, 16
+; GFX11-NEXT: s_lshr_b32 s5, s1, 24
+; GFX11-NEXT: s_lshl_b32 s4, s4, 0x80008
+; GFX11-NEXT: s_lshl_b32 s6, s6, 8
+; GFX11-NEXT: s_pack_hl_b32_b16 s0, s0, s3
+; GFX11-NEXT: s_pack_hl_b32_b16 s1, s1, s5
+; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s6
+; GFX11-NEXT: s_lshr_b32 s3, s0, 16
+; GFX11-NEXT: s_lshr_b32 s5, s1, 16
+; GFX11-NEXT: v_pk_add_i16 v0, s2, s4 clamp
+; GFX11-NEXT: s_lshl_b32 s0, s0, 0x80008
+; GFX11-NEXT: s_lshl_b32 s3, s3, 8
+; GFX11-NEXT: s_lshl_b32 s1, s1, 0x80008
+; GFX11-NEXT: s_lshl_b32 s2, s5, 8
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s3
+; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s2
+; GFX11-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_i16 v1, s0, s1 clamp
+; GFX11-NEXT: v_bfe_u32 v2, v0, 16, 8
+; GFX11-NEXT: v_pk_ashrrev_i16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v1
+; GFX11-NEXT: v_bfe_u32 v1, v1, 16, 8
+; GFX11-NEXT: v_and_or_b32 v0, v0, 0xff, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; GFX11-NEXT: v_or3_b32 v0, v0, v2, v1
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: ; return to shader part epilog
%lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8>
%result = call <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
@@ -942,15 +1065,15 @@ define i24 @v_saddsat_i24(i24 %lhs, i24 %rhs) {
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 8, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_saddsat_i24:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX10-NEXT: v_add_nc_i32 v0, v0, v1 clamp
-; GFX10-NEXT: v_ashrrev_i32_e32 v0, 8, v0
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_i24:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX10PLUS-NEXT: v_add_nc_i32 v0, v0, v1 clamp
+; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, 8, v0
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call i24 @llvm.sadd.sat.i24(i24 %lhs, i24 %rhs)
ret i24 %result
}
@@ -998,14 +1121,14 @@ define amdgpu_ps i24 @s_saddsat_i24(i24 inreg %lhs, i24 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_saddsat_i24:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_lshl_b32 s0, s0, 8
-; GFX10-NEXT: s_lshl_b32 s1, s1, 8
-; GFX10-NEXT: v_add_nc_i32 v0, s0, s1 clamp
-; GFX10-NEXT: v_ashrrev_i32_e32 v0, 8, v0
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_i24:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, 8
+; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, 8
+; GFX10PLUS-NEXT: v_add_nc_i32 v0, s0, s1 clamp
+; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, 8, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i24 @llvm.sadd.sat.i24(i24 %lhs, i24 %rhs)
ret i24 %result
}
@@ -1041,12 +1164,12 @@ define i32 @v_saddsat_i32(i32 %lhs, i32 %rhs) {
; GFX9-NEXT: v_add_i32 v0, v0, v1 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_saddsat_i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_add_nc_i32 v0, v0, v1 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_add_nc_i32 v0, v0, v1 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs)
ret i32 %result
}
@@ -1095,11 +1218,11 @@ define amdgpu_ps i32 @s_saddsat_i32(i32 inreg %lhs, i32 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_saddsat_i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_nc_i32 v0, s0, s1 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_nc_i32 v0, s0, s1 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs)
ret i32 %result
}
@@ -1132,10 +1255,10 @@ define amdgpu_ps float @saddsat_i32_sv(i32 inreg %lhs, i32 %rhs) {
; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: saddsat_i32_sv:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_nc_i32 v0, s0, v0 clamp
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: saddsat_i32_sv:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_nc_i32 v0, s0, v0 clamp
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs)
%cast = bitcast i32 %result to float
ret float %cast
@@ -1169,10 +1292,10 @@ define amdgpu_ps float @saddsat_i32_vs(i32 %lhs, i32 inreg %rhs) {
; GFX9-NEXT: v_add_i32 v0, v0, s0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: saddsat_i32_vs:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_nc_i32 v0, v0, s0 clamp
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: saddsat_i32_vs:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_nc_i32 v0, v0, s0 clamp
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs)
%cast = bitcast i32 %result to float
ret float %cast
@@ -1228,13 +1351,13 @@ define <2 x i32> @v_saddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
; GFX9-NEXT: v_add_i32 v1, v1, v3 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_saddsat_v2i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_add_nc_i32 v0, v0, v2 clamp
-; GFX10-NEXT: v_add_nc_i32 v1, v1, v3 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_v2i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_add_nc_i32 v0, v0, v2 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v1, v1, v3 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
ret <2 x i32> %result
}
@@ -1286,13 +1409,13 @@ define amdgpu_ps <2 x i32> @s_saddsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inre
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_saddsat_v2i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_nc_i32 v0, s0, s2 clamp
-; GFX10-NEXT: v_add_nc_i32 v1, s1, s3 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_v2i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_nc_i32 v0, s0, s2 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v1, s1, s3 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
ret <2 x i32> %result
}
@@ -1362,14 +1485,14 @@ define <3 x i32> @v_saddsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
; GFX9-NEXT: v_add_i32 v2, v2, v5 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_saddsat_v3i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_add_nc_i32 v0, v0, v3 clamp
-; GFX10-NEXT: v_add_nc_i32 v1, v1, v4 clamp
-; GFX10-NEXT: v_add_nc_i32 v2, v2, v5 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_v3i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_add_nc_i32 v0, v0, v3 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v1, v1, v4 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v2, v2, v5 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x i32> @llvm.sadd.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
ret <3 x i32> %result
}
@@ -1438,15 +1561,15 @@ define amdgpu_ps <3 x i32> @s_saddsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inre
; GFX9-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_saddsat_v3i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_nc_i32 v0, s0, s3 clamp
-; GFX10-NEXT: v_add_nc_i32 v1, s1, s4 clamp
-; GFX10-NEXT: v_add_nc_i32 v2, s2, s5 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_v3i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_nc_i32 v0, s0, s3 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v1, s1, s4 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v2, s2, s5 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <3 x i32> @llvm.sadd.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
ret <3 x i32> %result
}
@@ -1531,15 +1654,15 @@ define <4 x i32> @v_saddsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; GFX9-NEXT: v_add_i32 v3, v3, v7 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_saddsat_v4i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_add_nc_i32 v0, v0, v4 clamp
-; GFX10-NEXT: v_add_nc_i32 v1, v1, v5 clamp
-; GFX10-NEXT: v_add_nc_i32 v2, v2, v6 clamp
-; GFX10-NEXT: v_add_nc_i32 v3, v3, v7 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_v4i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_add_nc_i32 v0, v0, v4 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v1, v1, v5 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v2, v2, v6 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v3, v3, v7 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
ret <4 x i32> %result
}
@@ -1625,17 +1748,17 @@ define amdgpu_ps <4 x i32> @s_saddsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inre
; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_saddsat_v4i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_nc_i32 v0, s0, s4 clamp
-; GFX10-NEXT: v_add_nc_i32 v1, s1, s5 clamp
-; GFX10-NEXT: v_add_nc_i32 v2, s2, s6 clamp
-; GFX10-NEXT: v_add_nc_i32 v3, s3, s7 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_v4i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_nc_i32 v0, s0, s4 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v1, s1, s5 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v2, s2, s6 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v3, s3, s7 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
ret <4 x i32> %result
}
@@ -1737,16 +1860,16 @@ define <5 x i32> @v_saddsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
; GFX9-NEXT: v_add_i32 v4, v4, v9 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_saddsat_v5i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_add_nc_i32 v0, v0, v5 clamp
-; GFX10-NEXT: v_add_nc_i32 v1, v1, v6 clamp
-; GFX10-NEXT: v_add_nc_i32 v2, v2, v7 clamp
-; GFX10-NEXT: v_add_nc_i32 v3, v3, v8 clamp
-; GFX10-NEXT: v_add_nc_i32 v4, v4, v9 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_v5i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_add_nc_i32 v0, v0, v5 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v1, v1, v6 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v2, v2, v7 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v3, v3, v8 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v4, v4, v9 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <5 x i32> @llvm.sadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
ret <5 x i32> %result
}
@@ -1849,19 +1972,19 @@ define amdgpu_ps <5 x i32> @s_saddsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inre
; GFX9-NEXT: v_readfirstlane_b32 s4, v4
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_saddsat_v5i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_nc_i32 v0, s0, s5 clamp
-; GFX10-NEXT: v_add_nc_i32 v1, s1, s6 clamp
-; GFX10-NEXT: v_add_nc_i32 v2, s2, s7 clamp
-; GFX10-NEXT: v_add_nc_i32 v3, s3, s8 clamp
-; GFX10-NEXT: v_add_nc_i32 v4, s4, s9 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: v_readfirstlane_b32 s4, v4
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_v5i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_nc_i32 v0, s0, s5 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v1, s1, s6 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v2, s2, s7 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v3, s3, s8 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v4, s4, s9 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v4
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <5 x i32> @llvm.sadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
ret <5 x i32> %result
}
@@ -2159,6 +2282,30 @@ define <16 x i32> @v_saddsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_nc_i32 v15, v15, v31 clamp
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_saddsat_v16i32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_b32 v31, off, s32
+; GFX11-NEXT: v_add_nc_i32 v0, v0, v16 clamp
+; GFX11-NEXT: v_add_nc_i32 v1, v1, v17 clamp
+; GFX11-NEXT: v_add_nc_i32 v2, v2, v18 clamp
+; GFX11-NEXT: v_add_nc_i32 v3, v3, v19 clamp
+; GFX11-NEXT: v_add_nc_i32 v4, v4, v20 clamp
+; GFX11-NEXT: v_add_nc_i32 v5, v5, v21 clamp
+; GFX11-NEXT: v_add_nc_i32 v6, v6, v22 clamp
+; GFX11-NEXT: v_add_nc_i32 v7, v7, v23 clamp
+; GFX11-NEXT: v_add_nc_i32 v8, v8, v24 clamp
+; GFX11-NEXT: v_add_nc_i32 v9, v9, v25 clamp
+; GFX11-NEXT: v_add_nc_i32 v10, v10, v26 clamp
+; GFX11-NEXT: v_add_nc_i32 v11, v11, v27 clamp
+; GFX11-NEXT: v_add_nc_i32 v12, v12, v28 clamp
+; GFX11-NEXT: v_add_nc_i32 v13, v13, v29 clamp
+; GFX11-NEXT: v_add_nc_i32 v14, v14, v30 clamp
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_add_nc_i32 v15, v15, v31 clamp
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result
}
@@ -2448,41 +2595,41 @@ define amdgpu_ps <16 x i32> @s_saddsat_v16i32(<16 x i32> inreg %lhs, <16 x i32>
; GFX9-NEXT: v_readfirstlane_b32 s15, v15
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_saddsat_v16i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_nc_i32 v0, s0, s16 clamp
-; GFX10-NEXT: v_add_nc_i32 v1, s1, s17 clamp
-; GFX10-NEXT: v_add_nc_i32 v2, s2, s18 clamp
-; GFX10-NEXT: v_add_nc_i32 v3, s3, s19 clamp
-; GFX10-NEXT: v_add_nc_i32 v4, s4, s20 clamp
-; GFX10-NEXT: v_add_nc_i32 v5, s5, s21 clamp
-; GFX10-NEXT: v_add_nc_i32 v6, s6, s22 clamp
-; GFX10-NEXT: v_add_nc_i32 v7, s7, s23 clamp
-; GFX10-NEXT: v_add_nc_i32 v8, s8, s24 clamp
-; GFX10-NEXT: v_add_nc_i32 v9, s9, s25 clamp
-; GFX10-NEXT: v_add_nc_i32 v10, s10, s26 clamp
-; GFX10-NEXT: v_add_nc_i32 v11, s11, s27 clamp
-; GFX10-NEXT: v_add_nc_i32 v12, s12, s28 clamp
-; GFX10-NEXT: v_add_nc_i32 v13, s13, s29 clamp
-; GFX10-NEXT: v_add_nc_i32 v14, s14, s30 clamp
-; GFX10-NEXT: v_add_nc_i32 v15, s15, s31 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: v_readfirstlane_b32 s4, v4
-; GFX10-NEXT: v_readfirstlane_b32 s5, v5
-; GFX10-NEXT: v_readfirstlane_b32 s6, v6
-; GFX10-NEXT: v_readfirstlane_b32 s7, v7
-; GFX10-NEXT: v_readfirstlane_b32 s8, v8
-; GFX10-NEXT: v_readfirstlane_b32 s9, v9
-; GFX10-NEXT: v_readfirstlane_b32 s10, v10
-; GFX10-NEXT: v_readfirstlane_b32 s11, v11
-; GFX10-NEXT: v_readfirstlane_b32 s12, v12
-; GFX10-NEXT: v_readfirstlane_b32 s13, v13
-; GFX10-NEXT: v_readfirstlane_b32 s14, v14
-; GFX10-NEXT: v_readfirstlane_b32 s15, v15
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_v16i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_nc_i32 v0, s0, s16 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v1, s1, s17 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v2, s2, s18 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v3, s3, s19 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v4, s4, s20 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v5, s5, s21 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v6, s6, s22 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v7, s7, s23 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v8, s8, s24 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v9, s9, s25 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v10, s10, s26 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v11, s11, s27 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v12, s12, s28 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v13, s13, s29 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v14, s14, s30 clamp
+; GFX10PLUS-NEXT: v_add_nc_i32 v15, s15, s31 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v4
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s5, v5
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s6, v6
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s7, v7
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s8, v8
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s9, v9
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s10, v10
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s11, v11
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s12, v12
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s13, v13
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s14, v14
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s15, v15
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result
}
@@ -2521,12 +2668,12 @@ define i16 @v_saddsat_i16(i16 %lhs, i16 %rhs) {
; GFX9-NEXT: v_add_i16 v0, v0, v1 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_saddsat_i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_add_nc_i16 v0, v0, v1 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_add_nc_i16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result
}
@@ -2570,11 +2717,11 @@ define amdgpu_ps i16 @s_saddsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_saddsat_i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_nc_i16 v0, s0, s1 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_nc_i16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result
}
@@ -2612,10 +2759,10 @@ define amdgpu_ps half @saddsat_i16_sv(i16 inreg %lhs, i16 %rhs) {
; GFX9-NEXT: v_add_i16 v0, s0, v0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: saddsat_i16_sv:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_nc_i16 v0, s0, v0 clamp
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: saddsat_i16_sv:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_nc_i16 v0, s0, v0 clamp
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs)
%cast = bitcast i16 %result to half
ret half %cast
@@ -2652,10 +2799,10 @@ define amdgpu_ps half @saddsat_i16_vs(i16 %lhs, i16 inreg %rhs) {
; GFX9-NEXT: v_add_i16 v0, v0, s0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: saddsat_i16_vs:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_nc_i16 v0, v0, s0 clamp
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: saddsat_i16_vs:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_nc_i16 v0, v0, s0 clamp
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs)
%cast = bitcast i16 %result to half
ret half %cast
@@ -2716,12 +2863,12 @@ define <2 x i16> @v_saddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX9-NEXT: v_pk_add_i16 v0, v0, v1 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_saddsat_v2i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_add_i16 v0, v0, v1 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_v2i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_pk_add_i16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
ret <2 x i16> %result
}
@@ -2797,11 +2944,11 @@ define amdgpu_ps i32 @s_saddsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_saddsat_v2i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_add_i16 v0, s0, s1 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_v2i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_pk_add_i16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to i32
ret i32 %cast
@@ -2866,10 +3013,10 @@ define amdgpu_ps float @saddsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {
; GFX9-NEXT: v_pk_add_i16 v0, s0, v0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: saddsat_v2i16_sv:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_add_i16 v0, s0, v0 clamp
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: saddsat_v2i16_sv:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_pk_add_i16 v0, s0, v0 clamp
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to float
ret float %cast
@@ -2932,10 +3079,10 @@ define amdgpu_ps float @saddsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
; GFX9-NEXT: v_pk_add_i16 v0, v0, s0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: saddsat_v2i16_vs:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_add_i16 v0, v0, s0 clamp
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: saddsat_v2i16_vs:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_pk_add_i16 v0, v0, s0 clamp
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to float
ret float %cast
@@ -3054,13 +3201,13 @@ define <2 x float> @v_saddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX9-NEXT: v_pk_add_i16 v1, v1, v3 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_saddsat_v4i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_add_i16 v0, v0, v2 clamp
-; GFX10-NEXT: v_pk_add_i16 v1, v1, v3 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_v4i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_pk_add_i16 v0, v0, v2 clamp
+; GFX10PLUS-NEXT: v_pk_add_i16 v1, v1, v3 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
%cast = bitcast <4 x i16> %result to <2 x float>
ret <2 x float> %cast
@@ -3194,13 +3341,13 @@ define amdgpu_ps <2 x i32> @s_saddsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inre
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_saddsat_v4i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_add_i16 v0, s0, s2 clamp
-; GFX10-NEXT: v_pk_add_i16 v1, s1, s3 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_v4i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_pk_add_i16 v0, s0, s2 clamp
+; GFX10PLUS-NEXT: v_pk_add_i16 v1, s1, s3 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
%cast = bitcast <4 x i16> %result to <2 x i32>
ret <2 x i32> %cast
@@ -3360,14 +3507,14 @@ define <3 x float> @v_saddsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX9-NEXT: v_pk_add_i16 v2, v2, v5 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_saddsat_v6i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_add_i16 v0, v0, v3 clamp
-; GFX10-NEXT: v_pk_add_i16 v1, v1, v4 clamp
-; GFX10-NEXT: v_pk_add_i16 v2, v2, v5 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_v6i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_pk_add_i16 v0, v0, v3 clamp
+; GFX10PLUS-NEXT: v_pk_add_i16 v1, v1, v4 clamp
+; GFX10PLUS-NEXT: v_pk_add_i16 v2, v2, v5 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <6 x i16> @llvm.sadd.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
%cast = bitcast <6 x i16> %result to <3 x float>
ret <3 x float> %cast
@@ -3558,15 +3705,15 @@ define amdgpu_ps <3 x i32> @s_saddsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inre
; GFX9-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_saddsat_v6i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_add_i16 v0, s0, s3 clamp
-; GFX10-NEXT: v_pk_add_i16 v1, s1, s4 clamp
-; GFX10-NEXT: v_pk_add_i16 v2, s2, s5 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_v6i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_pk_add_i16 v0, s0, s3 clamp
+; GFX10PLUS-NEXT: v_pk_add_i16 v1, s1, s4 clamp
+; GFX10PLUS-NEXT: v_pk_add_i16 v2, s2, s5 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <6 x i16> @llvm.sadd.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
%cast = bitcast <6 x i16> %result to <3 x i32>
ret <3 x i32> %cast
@@ -3756,15 +3903,15 @@ define <4 x float> @v_saddsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
; GFX9-NEXT: v_pk_add_i16 v3, v3, v7 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_saddsat_v8i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_add_i16 v0, v0, v4 clamp
-; GFX10-NEXT: v_pk_add_i16 v1, v1, v5 clamp
-; GFX10-NEXT: v_pk_add_i16 v2, v2, v6 clamp
-; GFX10-NEXT: v_pk_add_i16 v3, v3, v7 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_saddsat_v8i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_pk_add_i16 v0, v0, v4 clamp
+; GFX10PLUS-NEXT: v_pk_add_i16 v1, v1, v5 clamp
+; GFX10PLUS-NEXT: v_pk_add_i16 v2, v2, v6 clamp
+; GFX10PLUS-NEXT: v_pk_add_i16 v3, v3, v7 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
%cast = bitcast <8 x i16> %result to <4 x float>
ret <4 x float> %cast
@@ -4012,17 +4159,17 @@ define amdgpu_ps <4 x i32> @s_saddsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inre
; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_saddsat_v8i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_add_i16 v0, s0, s4 clamp
-; GFX10-NEXT: v_pk_add_i16 v1, s1, s5 clamp
-; GFX10-NEXT: v_pk_add_i16 v2, s2, s6 clamp
-; GFX10-NEXT: v_pk_add_i16 v3, s3, s7 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_v8i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_pk_add_i16 v0, s0, s4 clamp
+; GFX10PLUS-NEXT: v_pk_add_i16 v1, s1, s5 clamp
+; GFX10PLUS-NEXT: v_pk_add_i16 v2, s2, s6 clamp
+; GFX10PLUS-NEXT: v_pk_add_i16 v3, s3, s7 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
%cast = bitcast <8 x i16> %result to <4 x i32>
ret <4 x i32> %cast
@@ -4117,6 +4264,22 @@ define i64 @v_saddsat_i64(i64 %lhs, i64 %rhs) {
; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_saddsat_i64:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v0, v2
+; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo
+; GFX11-NEXT: v_cmp_gt_i64_e64 s0, 0, v[2:3]
+; GFX11-NEXT: s_mov_b32 s1, 0
+; GFX11-NEXT: v_ashrrev_i32_e32 v6, 31, v5
+; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1]
+; GFX11-NEXT: v_add_co_ci_u32_e64 v1, s1, 0x80000000, v6, s1
+; GFX11-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i64 @llvm.sadd.sat.i64(i64 %lhs, i64 %rhs)
ret i64 %result
}
@@ -4191,24 +4354,24 @@ define amdgpu_ps i64 @s_saddsat_i64(i64 inreg %lhs, i64 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_saddsat_i64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_add_u32 s4, s0, s2
-; GFX10-NEXT: s_addc_u32 s5, s1, s3
-; GFX10-NEXT: v_cmp_lt_i64_e64 s2, s[2:3], 0
-; GFX10-NEXT: v_cmp_lt_i64_e64 s1, s[4:5], s[0:1]
-; GFX10-NEXT: s_mov_b32 s3, 0
-; GFX10-NEXT: s_ashr_i32 s0, s5, 31
-; GFX10-NEXT: v_mov_b32_e32 v0, s4
-; GFX10-NEXT: v_mov_b32_e32 v1, s5
-; GFX10-NEXT: s_xor_b32 s2, s2, s1
-; GFX10-NEXT: s_cmp_lg_u32 s3, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s0, s2
-; GFX10-NEXT: s_addc_u32 s1, s0, 0x80000000
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s1, s2
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_i64:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_add_u32 s4, s0, s2
+; GFX10PLUS-NEXT: s_addc_u32 s5, s1, s3
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s2, s[2:3], 0
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s1, s[4:5], s[0:1]
+; GFX10PLUS-NEXT: s_mov_b32 s3, 0
+; GFX10PLUS-NEXT: s_ashr_i32 s0, s5, 31
+; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s4
+; GFX10PLUS-NEXT: v_mov_b32_e32 v1, s5
+; GFX10PLUS-NEXT: s_xor_b32 s2, s2, s1
+; GFX10PLUS-NEXT: s_cmp_lg_u32 s3, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, s0, s2
+; GFX10PLUS-NEXT: s_addc_u32 s1, s0, 0x80000000
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s1, s2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i64 @llvm.sadd.sat.i64(i64 %lhs, i64 %rhs)
ret i64 %result
}
@@ -4262,19 +4425,19 @@ define amdgpu_ps <2 x float> @saddsat_i64_sv(i64 inreg %lhs, i64 %rhs) {
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: saddsat_i64_sv:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, s0, v0
-; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v3
-; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_gt_i64_e64 s0, 0, v[0:1]
-; GFX10-NEXT: s_mov_b32 s1, 0
-; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s1, 0x80000000, v4, s1
-; GFX10-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: saddsat_i64_sv:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_co_u32 v2, vcc_lo, s0, v0
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v4, 31, v3
+; GFX10PLUS-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[2:3]
+; GFX10PLUS-NEXT: v_cmp_gt_i64_e64 s0, 0, v[0:1]
+; GFX10PLUS-NEXT: s_mov_b32 s1, 0
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e64 v1, s1, 0x80000000, v4, s1
+; GFX10PLUS-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i64 @llvm.sadd.sat.i64(i64 %lhs, i64 %rhs)
%cast = bitcast i64 %result to <2 x float>
ret <2 x float> %cast
@@ -4329,19 +4492,19 @@ define amdgpu_ps <2 x float> @saddsat_i64_vs(i64 %lhs, i64 inreg %rhs) {
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: saddsat_i64_vs:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v0, s0
-; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT: v_cmp_lt_i64_e64 s1, s[0:1], 0
-; GFX10-NEXT: s_mov_b32 s0, 0
-; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v3
-; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]
-; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, 0x80000000, v4, s0
-; GFX10-NEXT: s_xor_b32 vcc_lo, s1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: saddsat_i64_vs:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_co_u32 v2, vcc_lo, v0, s0
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s1, s[0:1], 0
+; GFX10PLUS-NEXT: s_mov_b32 s0, 0
+; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v4, 31, v3
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e64 v1, s0, 0x80000000, v4, s0
+; GFX10PLUS-NEXT: s_xor_b32 vcc_lo, s1, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i64 @llvm.sadd.sat.i64(i64 %lhs, i64 %rhs)
%cast = bitcast i64 %result to <2 x float>
ret <2 x float> %cast
@@ -4447,6 +4610,31 @@ define <2 x i64> @v_saddsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_saddsat_v2i64:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v0, v4
+; GFX11-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v1, v5, vcc_lo
+; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v2, v6
+; GFX11-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, v3, v7, vcc_lo
+; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[0:1]
+; GFX11-NEXT: v_ashrrev_i32_e32 v0, 31, v9
+; GFX11-NEXT: s_mov_b32 s1, 0
+; GFX11-NEXT: v_cmp_gt_i64_e64 s0, 0, v[4:5]
+; GFX11-NEXT: v_ashrrev_i32_e32 v4, 31, v11
+; GFX11-NEXT: v_cmp_gt_i64_e64 s3, 0, v[6:7]
+; GFX11-NEXT: v_add_co_ci_u32_e64 v1, s2, 0x80000000, v0, s1
+; GFX11-NEXT: v_cmp_lt_i64_e64 s2, v[10:11], v[2:3]
+; GFX11-NEXT: v_add_co_ci_u32_e64 v3, s1, 0x80000000, v4, s1
+; GFX11-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
+; GFX11-NEXT: s_xor_b32 vcc_lo, s3, s2
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v10, v4, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
ret <2 x i64> %result
}
@@ -4578,38 +4766,38 @@ define amdgpu_ps <2 x i64> @s_saddsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inre
; GFX9-NEXT: v_readfirstlane_b32 s3, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_saddsat_v2i64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_add_u32 s8, s0, s4
-; GFX10-NEXT: s_addc_u32 s9, s1, s5
-; GFX10-NEXT: v_cmp_lt_i64_e64 s4, s[4:5], 0
-; GFX10-NEXT: v_cmp_lt_i64_e64 s1, s[8:9], s[0:1]
-; GFX10-NEXT: s_mov_b32 s10, 0
-; GFX10-NEXT: s_ashr_i32 s0, s9, 31
-; GFX10-NEXT: v_mov_b32_e32 v0, s8
-; GFX10-NEXT: v_mov_b32_e32 v1, s9
-; GFX10-NEXT: s_xor_b32 s8, s4, s1
-; GFX10-NEXT: s_cmp_lg_u32 s10, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s0, s8
-; GFX10-NEXT: s_addc_u32 s1, s0, 0x80000000
-; GFX10-NEXT: s_add_u32 s4, s2, s6
-; GFX10-NEXT: s_addc_u32 s5, s3, s7
-; GFX10-NEXT: v_mov_b32_e32 v2, s4
-; GFX10-NEXT: v_cmp_lt_i64_e64 s2, s[4:5], s[2:3]
-; GFX10-NEXT: v_cmp_lt_i64_e64 s3, s[6:7], 0
-; GFX10-NEXT: s_ashr_i32 s0, s5, 31
-; GFX10-NEXT: v_mov_b32_e32 v3, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s1, s8
-; GFX10-NEXT: s_xor_b32 s2, s3, s2
-; GFX10-NEXT: s_cmp_lg_u32 s10, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s0, s2
-; GFX10-NEXT: s_addc_u32 s1, s0, 0x80000000
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s1, s2
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_v2i64:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_add_u32 s8, s0, s4
+; GFX10PLUS-NEXT: s_addc_u32 s9, s1, s5
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s4, s[4:5], 0
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s1, s[8:9], s[0:1]
+; GFX10PLUS-NEXT: s_mov_b32 s10, 0
+; GFX10PLUS-NEXT: s_ashr_i32 s0, s9, 31
+; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s8
+; GFX10PLUS-NEXT: v_mov_b32_e32 v1, s9
+; GFX10PLUS-NEXT: s_xor_b32 s8, s4, s1
+; GFX10PLUS-NEXT: s_cmp_lg_u32 s10, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, s0, s8
+; GFX10PLUS-NEXT: s_addc_u32 s1, s0, 0x80000000
+; GFX10PLUS-NEXT: s_add_u32 s4, s2, s6
+; GFX10PLUS-NEXT: s_addc_u32 s5, s3, s7
+; GFX10PLUS-NEXT: v_mov_b32_e32 v2, s4
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s2, s[4:5], s[2:3]
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s3, s[6:7], 0
+; GFX10PLUS-NEXT: s_ashr_i32 s0, s5, 31
+; GFX10PLUS-NEXT: v_mov_b32_e32 v3, s5
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s1, s8
+; GFX10PLUS-NEXT: s_xor_b32 s2, s3, s2
+; GFX10PLUS-NEXT: s_cmp_lg_u32 s10, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, v2, s0, s2
+; GFX10PLUS-NEXT: s_addc_u32 s1, s0, 0x80000000
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, v3, s1, s2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
ret <2 x i64> %result
}
@@ -4768,50 +4956,50 @@ define amdgpu_ps i128 @s_saddsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_saddsat_i128:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_add_u32 s4, s0, s4
-; GFX10-NEXT: s_addc_u32 s5, s1, s5
-; GFX10-NEXT: s_addc_u32 s8, s2, s6
-; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[4:5], s[0:1]
-; GFX10-NEXT: s_addc_u32 s9, s3, s7
-; GFX10-NEXT: s_cmp_eq_u64 s[8:9], s[2:3]
-; GFX10-NEXT: v_mov_b32_e32 v3, s9
-; GFX10-NEXT: s_cselect_b32 s10, 1, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[8:9], s[2:3]
-; GFX10-NEXT: v_cmp_lt_i64_e64 s2, s[6:7], 0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
-; GFX10-NEXT: s_and_b32 s0, 1, s10
-; GFX10-NEXT: s_cmp_eq_u64 s[6:7], 0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s2
-; GFX10-NEXT: s_cselect_b32 s1, 1, 0
-; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT: s_and_b32 s1, 1, s1
-; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s1
-; GFX10-NEXT: s_mov_b32 s1, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, 0, s0
-; GFX10-NEXT: s_ashr_i32 s0, s9, 31
-; GFX10-NEXT: s_cmp_lg_u32 s1, 0
-; GFX10-NEXT: v_mov_b32_e32 v2, s5
-; GFX10-NEXT: s_addc_u32 s1, s0, 0
-; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
-; GFX10-NEXT: v_mov_b32_e32 v1, s4
-; GFX10-NEXT: s_addc_u32 s2, s0, 0
-; GFX10-NEXT: s_addc_u32 s3, s0, 0x80000000
-; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_mov_b32_e32 v0, s8
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s3, vcc_lo
-; GFX10-NEXT: v_readfirstlane_b32 s0, v1
-; GFX10-NEXT: v_readfirstlane_b32 s1, v2
-; GFX10-NEXT: v_readfirstlane_b32 s2, v0
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_i128:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_add_u32 s4, s0, s4
+; GFX10PLUS-NEXT: s_addc_u32 s5, s1, s5
+; GFX10PLUS-NEXT: s_addc_u32 s8, s2, s6
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s0, s[4:5], s[0:1]
+; GFX10PLUS-NEXT: s_addc_u32 s9, s3, s7
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[8:9], s[2:3]
+; GFX10PLUS-NEXT: v_mov_b32_e32 v3, s9
+; GFX10PLUS-NEXT: s_cselect_b32 s10, 1, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s0, s[8:9], s[2:3]
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s2, s[6:7], 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX10PLUS-NEXT: s_and_b32 s0, 1, s10
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[6:7], 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, 0, 1, s2
+; GFX10PLUS-NEXT: s_cselect_b32 s1, 1, 0
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
+; GFX10PLUS-NEXT: s_and_b32 s1, 1, s1
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 s0, 0, s1
+; GFX10PLUS-NEXT: s_mov_b32 s1, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v2, 0, s0
+; GFX10PLUS-NEXT: s_ashr_i32 s0, s9, 31
+; GFX10PLUS-NEXT: s_cmp_lg_u32 s1, 0
+; GFX10PLUS-NEXT: v_mov_b32_e32 v2, s5
+; GFX10PLUS-NEXT: s_addc_u32 s1, s0, 0
+; GFX10PLUS-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX10PLUS-NEXT: v_mov_b32_e32 v1, s4
+; GFX10PLUS-NEXT: s_addc_u32 s2, s0, 0
+; GFX10PLUS-NEXT: s_addc_u32 s3, s0, 0x80000000
+; GFX10PLUS-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s8
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s0, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, v2, s1, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, v3, s3, vcc_lo
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i128 @llvm.sadd.sat.i128(i128 %lhs, i128 %rhs)
ret i128 %result
}
@@ -4919,35 +5107,35 @@ define amdgpu_ps <4 x float> @saddsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: saddsat_i128_sv:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, s0, v0
-; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, s2, v2, vcc_lo
-; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
-; GFX10-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
-; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[4:5]
-; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[4:5]
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
-; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v5
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc_lo
-; GFX10-NEXT: s_mov_b32 vcc_lo, 0
-; GFX10-NEXT: v_xor_b32_e32 v2, v2, v6
-; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, 0, v3, vcc_lo
-; GFX10-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v2
-; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo
-; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0x80000000, v3, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v3, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v6, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, v2, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, v7, s0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: saddsat_i128_sv:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_co_u32 v0, vcc_lo, s0, v0
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, s2, v2, vcc_lo
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[4:5]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[2:3]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[4:5]
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
+; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v3, 31, v5
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc_lo
+; GFX10PLUS-NEXT: s_mov_b32 vcc_lo, 0
+; GFX10PLUS-NEXT: v_xor_b32_e32 v2, v2, v6
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, 0, v3, vcc_lo
+; GFX10PLUS-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 s0, 0, v2
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0x80000000, v3, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, v3, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, v6, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, v4, v2, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, v5, v7, s0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i128 @llvm.sadd.sat.i128(i128 %lhs, i128 %rhs)
%cast = bitcast i128 %result to <4 x float>
ret <4 x float> %cast
@@ -5062,38 +5250,38 @@ define amdgpu_ps <4 x float> @saddsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: saddsat_i128_vs:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, s0
-; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
-; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
-; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[0:1]
-; GFX10-NEXT: s_cmp_eq_u64 s[2:3], 0
-; GFX10-NEXT: v_cmp_lt_i64_e64 s1, s[2:3], 0
-; GFX10-NEXT: s_cselect_b32 s0, 1, 0
-; GFX10-NEXT: s_and_b32 s0, 1, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s1
-; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v8, 0, s0
-; GFX10-NEXT: s_mov_b32 vcc_lo, 0
-; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
-; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v7
-; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v1, vcc_lo
-; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
-; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
-; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0x80000000, v1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v1, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v2, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v3, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v8, s0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: saddsat_i128_vs:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_co_u32 v4, vcc_lo, v0, s0
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[0:1]
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[2:3], 0
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s1, s[2:3], 0
+; GFX10PLUS-NEXT: s_cselect_b32 s0, 1, 0
+; GFX10PLUS-NEXT: s_and_b32 s0, 1, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[2:3]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v8, 0, 1, s1
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 s0, 0, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v8, 0, s0
+; GFX10PLUS-NEXT: s_mov_b32 vcc_lo, 0
+; GFX10PLUS-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v1, 31, v7
+; GFX10PLUS-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v1, vcc_lo
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0x80000000, v1, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v4, v1, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v5, v2, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, v6, v3, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, v7, v8, s0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i128 @llvm.sadd.sat.i128(i128 %lhs, i128 %rhs)
%cast = bitcast i128 %result to <4 x float>
ret <4 x float> %cast
@@ -5327,6 +5515,63 @@ define <2 x i128> @v_saddsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX10-NEXT: v_cndmask_b32_e64 v6, v12, v8, s4
; GFX10-NEXT: v_cndmask_b32_e64 v7, v13, v9, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_saddsat_v2i128:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v0, v8
+; GFX11-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v1, v9, vcc_lo
+; GFX11-NEXT: v_add_co_ci_u32_e32 v16, vcc_lo, v2, v10, vcc_lo
+; GFX11-NEXT: v_add_co_ci_u32_e32 v17, vcc_lo, v3, v11, vcc_lo
+; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[8:9], v[0:1]
+; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[16:17], v[2:3]
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[16:17], v[2:3]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v18, 0, vcc_lo
+; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v4, v12
+; GFX11-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, v5, v13, vcc_lo
+; GFX11-NEXT: v_add_co_ci_u32_e32 v12, vcc_lo, v6, v14, vcc_lo
+; GFX11-NEXT: v_add_co_ci_u32_e32 v13, vcc_lo, v7, v15, vcc_lo
+; GFX11-NEXT: v_cmp_lt_u64_e64 s1, v[10:11], v[4:5]
+; GFX11-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX11-NEXT: v_ashrrev_i32_e32 v1, 31, v17
+; GFX11-NEXT: v_cmp_eq_u64_e64 s2, v[12:13], v[6:7]
+; GFX11-NEXT: s_mov_b32 vcc_lo, 0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, s1
+; GFX11-NEXT: v_cmp_lt_i64_e64 s1, v[12:13], v[6:7]
+; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-NEXT: v_ashrrev_i32_e32 v6, 31, v13
+; GFX11-NEXT: v_add_co_ci_u32_e64 v2, s0, 0, v1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
+; GFX11-NEXT: v_cmp_gt_i64_e64 s1, 0, v[14:15]
+; GFX11-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v6, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 1, s1
+; GFX11-NEXT: v_cmp_ne_u32_e64 s1, 0, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, v3, s2
+; GFX11-NEXT: v_cmp_eq_u64_e64 s2, 0, v[14:15]
+; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s0, 0, v1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v5, 0, s2
+; GFX11-NEXT: v_add_co_ci_u32_e64 v5, s0, 0x80000000, v1, s0
+; GFX11-NEXT: v_xor_b32_e32 v3, v3, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v8, v1, s1
+; GFX11-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v6, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v9, v2, s1
+; GFX11-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX11-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0x80000000, v6, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v16, v4, s1
+; GFX11-NEXT: v_cmp_ne_u32_e64 s0, 0, v3
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v17, v5, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v10, v6, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v11, v7, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v12, v8, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v13, v9, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i128> @llvm.sadd.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
ret <2 x i128> %result
}
@@ -5626,91 +5871,91 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX9-NEXT: v_readfirstlane_b32 s7, v3
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_saddsat_v2i128:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_add_u32 s8, s0, s8
-; GFX10-NEXT: s_addc_u32 s9, s1, s9
-; GFX10-NEXT: s_addc_u32 s16, s2, s10
-; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[8:9], s[0:1]
-; GFX10-NEXT: s_addc_u32 s17, s3, s11
-; GFX10-NEXT: s_cmp_eq_u64 s[16:17], s[2:3]
-; GFX10-NEXT: v_mov_b32_e32 v5, s17
-; GFX10-NEXT: s_cselect_b32 s18, 1, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[16:17], s[2:3]
-; GFX10-NEXT: v_cmp_lt_i64_e64 s2, s[10:11], 0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
-; GFX10-NEXT: s_and_b32 s0, 1, s18
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s2
-; GFX10-NEXT: s_cselect_b32 s1, 1, 0
-; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT: s_and_b32 s1, 1, s1
-; GFX10-NEXT: s_ashr_i32 s2, s17, 31
-; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s1
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, 0, s0
-; GFX10-NEXT: s_mov_b32 s0, 0
-; GFX10-NEXT: s_cmp_lg_u32 s0, 0
-; GFX10-NEXT: s_addc_u32 s1, s2, 0
-; GFX10-NEXT: s_addc_u32 s10, s2, 0
-; GFX10-NEXT: s_addc_u32 s3, s2, 0x80000000
-; GFX10-NEXT: s_add_u32 s12, s4, s12
-; GFX10-NEXT: s_addc_u32 s13, s5, s13
-; GFX10-NEXT: s_addc_u32 s18, s6, s14
-; GFX10-NEXT: v_cmp_lt_u64_e64 s4, s[12:13], s[4:5]
-; GFX10-NEXT: s_addc_u32 s19, s7, s15
-; GFX10-NEXT: v_cmp_lt_i64_e64 s5, s[14:15], 0
-; GFX10-NEXT: s_cmp_eq_u64 s[18:19], s[6:7]
-; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
-; GFX10-NEXT: s_cselect_b32 s0, 1, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
-; GFX10-NEXT: v_cmp_lt_i64_e64 s4, s[18:19], s[6:7]
-; GFX10-NEXT: s_and_b32 s0, 1, s0
-; GFX10-NEXT: s_cmp_eq_u64 s[14:15], 0
-; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s5
-; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
-; GFX10-NEXT: s_cselect_b32 s4, 1, 0
-; GFX10-NEXT: v_mov_b32_e32 v1, s8
-; GFX10-NEXT: s_and_b32 s4, 1, s4
-; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v3, v2, s0
-; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s4
-; GFX10-NEXT: v_mov_b32_e32 v0, s9
-; GFX10-NEXT: v_mov_b32_e32 v6, s13
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s2, vcc_lo
-; GFX10-NEXT: v_mov_b32_e32 v7, s19
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v4, 0, s0
-; GFX10-NEXT: v_mov_b32_e32 v4, s16
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s1, vcc_lo
-; GFX10-NEXT: s_mov_b32 s1, 0
-; GFX10-NEXT: s_ashr_i32 s0, s19, 31
-; GFX10-NEXT: v_xor_b32_e32 v2, v3, v2
-; GFX10-NEXT: s_cmp_lg_u32 s1, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v4, s10, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v5, s3, vcc_lo
-; GFX10-NEXT: v_mov_b32_e32 v5, s12
-; GFX10-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX10-NEXT: s_addc_u32 s1, s0, 0
-; GFX10-NEXT: s_addc_u32 s2, s0, 0
-; GFX10-NEXT: s_addc_u32 s3, s0, 0x80000000
-; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX10-NEXT: v_mov_b32_e32 v2, s18
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, s1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, s3, vcc_lo
-; GFX10-NEXT: v_readfirstlane_b32 s0, v1
-; GFX10-NEXT: v_readfirstlane_b32 s1, v0
-; GFX10-NEXT: v_readfirstlane_b32 s2, v3
-; GFX10-NEXT: v_readfirstlane_b32 s3, v4
-; GFX10-NEXT: v_readfirstlane_b32 s4, v5
-; GFX10-NEXT: v_readfirstlane_b32 s5, v6
-; GFX10-NEXT: v_readfirstlane_b32 s6, v2
-; GFX10-NEXT: v_readfirstlane_b32 s7, v7
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_saddsat_v2i128:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_add_u32 s8, s0, s8
+; GFX10PLUS-NEXT: s_addc_u32 s9, s1, s9
+; GFX10PLUS-NEXT: s_addc_u32 s16, s2, s10
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s0, s[8:9], s[0:1]
+; GFX10PLUS-NEXT: s_addc_u32 s17, s3, s11
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[16:17], s[2:3]
+; GFX10PLUS-NEXT: v_mov_b32_e32 v5, s17
+; GFX10PLUS-NEXT: s_cselect_b32 s18, 1, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s0, s[16:17], s[2:3]
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s2, s[10:11], 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX10PLUS-NEXT: s_and_b32 s0, 1, s18
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, 0, 1, s2
+; GFX10PLUS-NEXT: s_cselect_b32 s1, 1, 0
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
+; GFX10PLUS-NEXT: s_and_b32 s1, 1, s1
+; GFX10PLUS-NEXT: s_ashr_i32 s2, s17, 31
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 s0, 0, s1
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v2, 0, s0
+; GFX10PLUS-NEXT: s_mov_b32 s0, 0
+; GFX10PLUS-NEXT: s_cmp_lg_u32 s0, 0
+; GFX10PLUS-NEXT: s_addc_u32 s1, s2, 0
+; GFX10PLUS-NEXT: s_addc_u32 s10, s2, 0
+; GFX10PLUS-NEXT: s_addc_u32 s3, s2, 0x80000000
+; GFX10PLUS-NEXT: s_add_u32 s12, s4, s12
+; GFX10PLUS-NEXT: s_addc_u32 s13, s5, s13
+; GFX10PLUS-NEXT: s_addc_u32 s18, s6, s14
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s4, s[12:13], s[4:5]
+; GFX10PLUS-NEXT: s_addc_u32 s19, s7, s15
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s5, s[14:15], 0
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[18:19], s[6:7]
+; GFX10PLUS-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX10PLUS-NEXT: s_cselect_b32 s0, 1, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s4, s[18:19], s[6:7]
+; GFX10PLUS-NEXT: s_and_b32 s0, 1, s0
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[14:15], 0
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 s0, 0, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v4, 0, 1, s5
+; GFX10PLUS-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
+; GFX10PLUS-NEXT: s_cselect_b32 s4, 1, 0
+; GFX10PLUS-NEXT: v_mov_b32_e32 v1, s8
+; GFX10PLUS-NEXT: s_and_b32 s4, 1, s4
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, v3, v2, s0
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 s0, 0, s4
+; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s9
+; GFX10PLUS-NEXT: v_mov_b32_e32 v6, s13
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s2, vcc_lo
+; GFX10PLUS-NEXT: v_mov_b32_e32 v7, s19
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, v4, 0, s0
+; GFX10PLUS-NEXT: v_mov_b32_e32 v4, s16
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, s1, vcc_lo
+; GFX10PLUS-NEXT: s_mov_b32 s1, 0
+; GFX10PLUS-NEXT: s_ashr_i32 s0, s19, 31
+; GFX10PLUS-NEXT: v_xor_b32_e32 v2, v3, v2
+; GFX10PLUS-NEXT: s_cmp_lg_u32 s1, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, v4, s10, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v4, v5, s3, vcc_lo
+; GFX10PLUS-NEXT: v_mov_b32_e32 v5, s12
+; GFX10PLUS-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX10PLUS-NEXT: s_addc_u32 s1, s0, 0
+; GFX10PLUS-NEXT: s_addc_u32 s2, s0, 0
+; GFX10PLUS-NEXT: s_addc_u32 s3, s0, 0x80000000
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX10PLUS-NEXT: v_mov_b32_e32 v2, s18
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v5, v5, s0, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v6, v6, s1, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v7, v7, s3, vcc_lo
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v3
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v4
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v5
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s5, v6
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s6, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s7, v7
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <2 x i128> @llvm.sadd.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
ret <2 x i128> %result
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
index 78b620ec8f8d5..39d9393c37e21 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
@@ -2,7 +2,8 @@
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -o - %s | FileCheck -check-prefix=GFX6 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s | FileCheck -check-prefix=GFX8 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
define i7 @v_ssubsat_i7(i7 %lhs, i7 %rhs) {
; GFX6-LABEL: v_ssubsat_i7:
@@ -44,15 +45,15 @@ define i7 @v_ssubsat_i7(i7 %lhs, i7 %rhs) {
; GFX9-NEXT: v_ashrrev_i16_e32 v0, 9, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_ssubsat_i7:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_lshlrev_b16 v0, 9, v0
-; GFX10-NEXT: v_lshlrev_b16 v1, 9, v1
-; GFX10-NEXT: v_sub_nc_i16 v0, v0, v1 clamp
-; GFX10-NEXT: v_ashrrev_i16 v0, 9, v0
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_i7:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_lshlrev_b16 v0, 9, v0
+; GFX10PLUS-NEXT: v_lshlrev_b16 v1, 9, v1
+; GFX10PLUS-NEXT: v_sub_nc_i16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT: v_ashrrev_i16 v0, 9, v0
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call i7 @llvm.ssub.sat.i7(i7 %lhs, i7 %rhs)
ret i7 %result
}
@@ -105,15 +106,15 @@ define amdgpu_ps i7 @s_ssubsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_ssubsat_i7:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_bfe_u32 s2, 9, 0x100000
-; GFX10-NEXT: s_lshl_b32 s0, s0, s2
-; GFX10-NEXT: s_lshl_b32 s1, s1, s2
-; GFX10-NEXT: v_sub_nc_i16 v0, s0, s1 clamp
-; GFX10-NEXT: v_ashrrev_i16 v0, 9, v0
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_i7:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_bfe_u32 s2, 9, 0x100000
+; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, s2
+; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, s2
+; GFX10PLUS-NEXT: v_sub_nc_i16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT: v_ashrrev_i16 v0, 9, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i7 @llvm.ssub.sat.i7(i7 %lhs, i7 %rhs)
ret i7 %result
}
@@ -158,15 +159,15 @@ define i8 @v_ssubsat_i8(i8 %lhs, i8 %rhs) {
; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_ssubsat_i8:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_lshlrev_b16 v0, 8, v0
-; GFX10-NEXT: v_lshlrev_b16 v1, 8, v1
-; GFX10-NEXT: v_sub_nc_i16 v0, v0, v1 clamp
-; GFX10-NEXT: v_ashrrev_i16 v0, 8, v0
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_i8:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_lshlrev_b16 v0, 8, v0
+; GFX10PLUS-NEXT: v_lshlrev_b16 v1, 8, v1
+; GFX10PLUS-NEXT: v_sub_nc_i16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT: v_ashrrev_i16 v0, 8, v0
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs)
ret i8 %result
}
@@ -219,15 +220,15 @@ define amdgpu_ps i8 @s_ssubsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_ssubsat_i8:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_bfe_u32 s2, 8, 0x100000
-; GFX10-NEXT: s_lshl_b32 s0, s0, s2
-; GFX10-NEXT: s_lshl_b32 s1, s1, s2
-; GFX10-NEXT: v_sub_nc_i16 v0, s0, s1 clamp
-; GFX10-NEXT: v_ashrrev_i16 v0, 8, v0
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_i8:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_bfe_u32 s2, 8, 0x100000
+; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, s2
+; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, s2
+; GFX10PLUS-NEXT: v_sub_nc_i16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT: v_ashrrev_i16 v0, 8, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs)
ret i8 %result
}
@@ -329,6 +330,27 @@ define i16 @v_ssubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX10-NEXT: v_and_b32_sdwa v1, v0, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_ssubsat_v2i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_lshrrev_b32_e32 v2, 8, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT: v_and_or_b32 v0, 0xffff, v0, v2
+; GFX11-NEXT: v_and_or_b32 v1, 0xffff, v1, v3
+; GFX11-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_sub_i16 v0, v0, v1 clamp
+; GFX11-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8>
%result = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
@@ -455,6 +477,30 @@ define amdgpu_ps i16 @s_ssubsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_ssubsat_v2i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshr_b32 s2, s0, 8
+; GFX11-NEXT: s_lshr_b32 s3, s1, 8
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s2
+; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s3
+; GFX11-NEXT: s_lshr_b32 s2, s0, 16
+; GFX11-NEXT: s_lshr_b32 s3, s1, 16
+; GFX11-NEXT: s_lshl_b32 s0, s0, 0x80008
+; GFX11-NEXT: s_lshl_b32 s2, s2, 8
+; GFX11-NEXT: s_lshl_b32 s1, s1, 0x80008
+; GFX11-NEXT: s_lshl_b32 s3, s3, 8
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s2
+; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s3
+; GFX11-NEXT: v_pk_sub_i16 v0, s0, s1 clamp
+; GFX11-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: ; return to shader part epilog
%lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8>
%result = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
@@ -653,6 +699,42 @@ define i32 @v_ssubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX10-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_ssubsat_v4i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_lshrrev_b32_e32 v2, 8, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v5, 24, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v6, 24, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-NEXT: v_and_or_b32 v0, 0xffff, v0, v2
+; GFX11-NEXT: v_and_or_b32 v1, 0xffff, v1, v3
+; GFX11-NEXT: v_and_or_b32 v2, 0xffff, v4, v5
+; GFX11-NEXT: v_and_or_b32 v3, 0xffff, v7, v6
+; GFX11-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_sub_i16 v0, v0, v1 clamp
+; GFX11-NEXT: v_pk_sub_i16 v1, v2, v3 clamp
+; GFX11-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_ashrrev_i16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT: v_bfe_u32 v2, v0, 16, 8
+; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v1
+; GFX11-NEXT: v_bfe_u32 v1, v1, 16, 8
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; GFX11-NEXT: v_and_or_b32 v0, v0, 0xff, v2
+; GFX11-NEXT: v_or3_b32 v0, v0, v3, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8>
%result = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
@@ -895,6 +977,47 @@ define amdgpu_ps i32 @s_ssubsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) {
; GFX10-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_ssubsat_v4i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshr_b32 s2, s0, 8
+; GFX11-NEXT: s_lshr_b32 s4, s1, 8
+; GFX11-NEXT: s_pack_ll_b32_b16 s2, s0, s2
+; GFX11-NEXT: s_pack_ll_b32_b16 s4, s1, s4
+; GFX11-NEXT: s_lshr_b32 s6, s2, 16
+; GFX11-NEXT: s_lshl_b32 s2, s2, 0x80008
+; GFX11-NEXT: s_lshl_b32 s6, s6, 8
+; GFX11-NEXT: s_lshr_b32 s3, s0, 24
+; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s6
+; GFX11-NEXT: s_lshr_b32 s6, s4, 16
+; GFX11-NEXT: s_lshr_b32 s5, s1, 24
+; GFX11-NEXT: s_lshl_b32 s4, s4, 0x80008
+; GFX11-NEXT: s_lshl_b32 s6, s6, 8
+; GFX11-NEXT: s_pack_hl_b32_b16 s0, s0, s3
+; GFX11-NEXT: s_pack_hl_b32_b16 s1, s1, s5
+; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s6
+; GFX11-NEXT: s_lshr_b32 s3, s0, 16
+; GFX11-NEXT: s_lshr_b32 s5, s1, 16
+; GFX11-NEXT: v_pk_sub_i16 v0, s2, s4 clamp
+; GFX11-NEXT: s_lshl_b32 s0, s0, 0x80008
+; GFX11-NEXT: s_lshl_b32 s3, s3, 8
+; GFX11-NEXT: s_lshl_b32 s1, s1, 0x80008
+; GFX11-NEXT: s_lshl_b32 s2, s5, 8
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s3
+; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s2
+; GFX11-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_sub_i16 v1, s0, s1 clamp
+; GFX11-NEXT: v_bfe_u32 v2, v0, 16, 8
+; GFX11-NEXT: v_pk_ashrrev_i16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v1
+; GFX11-NEXT: v_bfe_u32 v1, v1, 16, 8
+; GFX11-NEXT: v_and_or_b32 v0, v0, 0xff, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; GFX11-NEXT: v_or3_b32 v0, v0, v2, v1
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: ; return to shader part epilog
%lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8>
%result = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
@@ -942,15 +1065,15 @@ define i24 @v_ssubsat_i24(i24 %lhs, i24 %rhs) {
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 8, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_ssubsat_i24:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX10-NEXT: v_sub_nc_i32 v0, v0, v1 clamp
-; GFX10-NEXT: v_ashrrev_i32_e32 v0, 8, v0
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_i24:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX10PLUS-NEXT: v_sub_nc_i32 v0, v0, v1 clamp
+; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, 8, v0
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call i24 @llvm.ssub.sat.i24(i24 %lhs, i24 %rhs)
ret i24 %result
}
@@ -998,14 +1121,14 @@ define amdgpu_ps i24 @s_ssubsat_i24(i24 inreg %lhs, i24 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_ssubsat_i24:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_lshl_b32 s0, s0, 8
-; GFX10-NEXT: s_lshl_b32 s1, s1, 8
-; GFX10-NEXT: v_sub_nc_i32 v0, s0, s1 clamp
-; GFX10-NEXT: v_ashrrev_i32_e32 v0, 8, v0
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_i24:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, 8
+; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, 8
+; GFX10PLUS-NEXT: v_sub_nc_i32 v0, s0, s1 clamp
+; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, 8, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i24 @llvm.ssub.sat.i24(i24 %lhs, i24 %rhs)
ret i24 %result
}
@@ -1041,12 +1164,12 @@ define i32 @v_ssubsat_i32(i32 %lhs, i32 %rhs) {
; GFX9-NEXT: v_sub_i32 v0, v0, v1 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_ssubsat_i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_sub_nc_i32 v0, v0, v1 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_sub_nc_i32 v0, v0, v1 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)
ret i32 %result
}
@@ -1081,11 +1204,11 @@ define amdgpu_ps i32 @s_ssubsat_i32(i32 inreg %lhs, i32 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_ssubsat_i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_nc_i32 v0, s0, s1 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_nc_i32 v0, s0, s1 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)
ret i32 %result
}
@@ -1118,10 +1241,10 @@ define amdgpu_ps float @ssubsat_i32_sv(i32 inreg %lhs, i32 %rhs) {
; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: ssubsat_i32_sv:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_nc_i32 v0, s0, v0 clamp
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: ssubsat_i32_sv:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_nc_i32 v0, s0, v0 clamp
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)
%cast = bitcast i32 %result to float
ret float %cast
@@ -1155,10 +1278,10 @@ define amdgpu_ps float @ssubsat_i32_vs(i32 %lhs, i32 inreg %rhs) {
; GFX9-NEXT: v_sub_i32 v0, v0, s0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: ssubsat_i32_vs:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_nc_i32 v0, v0, s0 clamp
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: ssubsat_i32_vs:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_nc_i32 v0, v0, s0 clamp
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)
%cast = bitcast i32 %result to float
ret float %cast
@@ -1214,13 +1337,13 @@ define <2 x i32> @v_ssubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
; GFX9-NEXT: v_sub_i32 v1, v1, v3 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_ssubsat_v2i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_sub_nc_i32 v0, v0, v2 clamp
-; GFX10-NEXT: v_sub_nc_i32 v1, v1, v3 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_v2i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_sub_nc_i32 v0, v0, v2 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v1, v1, v3 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
ret <2 x i32> %result
}
@@ -1272,13 +1395,13 @@ define amdgpu_ps <2 x i32> @s_ssubsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inre
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_ssubsat_v2i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_nc_i32 v0, s0, s2 clamp
-; GFX10-NEXT: v_sub_nc_i32 v1, s1, s3 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_v2i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_nc_i32 v0, s0, s2 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v1, s1, s3 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
ret <2 x i32> %result
}
@@ -1348,14 +1471,14 @@ define <3 x i32> @v_ssubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
; GFX9-NEXT: v_sub_i32 v2, v2, v5 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_ssubsat_v3i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_sub_nc_i32 v0, v0, v3 clamp
-; GFX10-NEXT: v_sub_nc_i32 v1, v1, v4 clamp
-; GFX10-NEXT: v_sub_nc_i32 v2, v2, v5 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_v3i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_sub_nc_i32 v0, v0, v3 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v1, v1, v4 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v2, v2, v5 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
ret <3 x i32> %result
}
@@ -1424,15 +1547,15 @@ define amdgpu_ps <3 x i32> @s_ssubsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inre
; GFX9-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_ssubsat_v3i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_nc_i32 v0, s0, s3 clamp
-; GFX10-NEXT: v_sub_nc_i32 v1, s1, s4 clamp
-; GFX10-NEXT: v_sub_nc_i32 v2, s2, s5 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_v3i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_nc_i32 v0, s0, s3 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v1, s1, s4 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v2, s2, s5 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
ret <3 x i32> %result
}
@@ -1517,15 +1640,15 @@ define <4 x i32> @v_ssubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; GFX9-NEXT: v_sub_i32 v3, v3, v7 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_ssubsat_v4i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_sub_nc_i32 v0, v0, v4 clamp
-; GFX10-NEXT: v_sub_nc_i32 v1, v1, v5 clamp
-; GFX10-NEXT: v_sub_nc_i32 v2, v2, v6 clamp
-; GFX10-NEXT: v_sub_nc_i32 v3, v3, v7 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_v4i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_sub_nc_i32 v0, v0, v4 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v1, v1, v5 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v2, v2, v6 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v3, v3, v7 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
ret <4 x i32> %result
}
@@ -1611,17 +1734,17 @@ define amdgpu_ps <4 x i32> @s_ssubsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inre
; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_ssubsat_v4i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_nc_i32 v0, s0, s4 clamp
-; GFX10-NEXT: v_sub_nc_i32 v1, s1, s5 clamp
-; GFX10-NEXT: v_sub_nc_i32 v2, s2, s6 clamp
-; GFX10-NEXT: v_sub_nc_i32 v3, s3, s7 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_v4i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_nc_i32 v0, s0, s4 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v1, s1, s5 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v2, s2, s6 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v3, s3, s7 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
ret <4 x i32> %result
}
@@ -1723,16 +1846,16 @@ define <5 x i32> @v_ssubsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
; GFX9-NEXT: v_sub_i32 v4, v4, v9 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_ssubsat_v5i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_sub_nc_i32 v0, v0, v5 clamp
-; GFX10-NEXT: v_sub_nc_i32 v1, v1, v6 clamp
-; GFX10-NEXT: v_sub_nc_i32 v2, v2, v7 clamp
-; GFX10-NEXT: v_sub_nc_i32 v3, v3, v8 clamp
-; GFX10-NEXT: v_sub_nc_i32 v4, v4, v9 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_v5i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_sub_nc_i32 v0, v0, v5 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v1, v1, v6 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v2, v2, v7 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v3, v3, v8 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v4, v4, v9 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <5 x i32> @llvm.ssub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
ret <5 x i32> %result
}
@@ -1835,19 +1958,19 @@ define amdgpu_ps <5 x i32> @s_ssubsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inre
; GFX9-NEXT: v_readfirstlane_b32 s4, v4
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_ssubsat_v5i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_nc_i32 v0, s0, s5 clamp
-; GFX10-NEXT: v_sub_nc_i32 v1, s1, s6 clamp
-; GFX10-NEXT: v_sub_nc_i32 v2, s2, s7 clamp
-; GFX10-NEXT: v_sub_nc_i32 v3, s3, s8 clamp
-; GFX10-NEXT: v_sub_nc_i32 v4, s4, s9 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: v_readfirstlane_b32 s4, v4
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_v5i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_nc_i32 v0, s0, s5 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v1, s1, s6 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v2, s2, s7 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v3, s3, s8 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v4, s4, s9 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v4
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <5 x i32> @llvm.ssub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
ret <5 x i32> %result
}
@@ -2145,6 +2268,30 @@ define <16 x i32> @v_ssubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_sub_nc_i32 v15, v15, v31 clamp
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_ssubsat_v16i32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_b32 v31, off, s32
+; GFX11-NEXT: v_sub_nc_i32 v0, v0, v16 clamp
+; GFX11-NEXT: v_sub_nc_i32 v1, v1, v17 clamp
+; GFX11-NEXT: v_sub_nc_i32 v2, v2, v18 clamp
+; GFX11-NEXT: v_sub_nc_i32 v3, v3, v19 clamp
+; GFX11-NEXT: v_sub_nc_i32 v4, v4, v20 clamp
+; GFX11-NEXT: v_sub_nc_i32 v5, v5, v21 clamp
+; GFX11-NEXT: v_sub_nc_i32 v6, v6, v22 clamp
+; GFX11-NEXT: v_sub_nc_i32 v7, v7, v23 clamp
+; GFX11-NEXT: v_sub_nc_i32 v8, v8, v24 clamp
+; GFX11-NEXT: v_sub_nc_i32 v9, v9, v25 clamp
+; GFX11-NEXT: v_sub_nc_i32 v10, v10, v26 clamp
+; GFX11-NEXT: v_sub_nc_i32 v11, v11, v27 clamp
+; GFX11-NEXT: v_sub_nc_i32 v12, v12, v28 clamp
+; GFX11-NEXT: v_sub_nc_i32 v13, v13, v29 clamp
+; GFX11-NEXT: v_sub_nc_i32 v14, v14, v30 clamp
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_sub_nc_i32 v15, v15, v31 clamp
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result
}
@@ -2434,41 +2581,41 @@ define amdgpu_ps <16 x i32> @s_ssubsat_v16i32(<16 x i32> inreg %lhs, <16 x i32>
; GFX9-NEXT: v_readfirstlane_b32 s15, v15
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_ssubsat_v16i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_nc_i32 v0, s0, s16 clamp
-; GFX10-NEXT: v_sub_nc_i32 v1, s1, s17 clamp
-; GFX10-NEXT: v_sub_nc_i32 v2, s2, s18 clamp
-; GFX10-NEXT: v_sub_nc_i32 v3, s3, s19 clamp
-; GFX10-NEXT: v_sub_nc_i32 v4, s4, s20 clamp
-; GFX10-NEXT: v_sub_nc_i32 v5, s5, s21 clamp
-; GFX10-NEXT: v_sub_nc_i32 v6, s6, s22 clamp
-; GFX10-NEXT: v_sub_nc_i32 v7, s7, s23 clamp
-; GFX10-NEXT: v_sub_nc_i32 v8, s8, s24 clamp
-; GFX10-NEXT: v_sub_nc_i32 v9, s9, s25 clamp
-; GFX10-NEXT: v_sub_nc_i32 v10, s10, s26 clamp
-; GFX10-NEXT: v_sub_nc_i32 v11, s11, s27 clamp
-; GFX10-NEXT: v_sub_nc_i32 v12, s12, s28 clamp
-; GFX10-NEXT: v_sub_nc_i32 v13, s13, s29 clamp
-; GFX10-NEXT: v_sub_nc_i32 v14, s14, s30 clamp
-; GFX10-NEXT: v_sub_nc_i32 v15, s15, s31 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: v_readfirstlane_b32 s4, v4
-; GFX10-NEXT: v_readfirstlane_b32 s5, v5
-; GFX10-NEXT: v_readfirstlane_b32 s6, v6
-; GFX10-NEXT: v_readfirstlane_b32 s7, v7
-; GFX10-NEXT: v_readfirstlane_b32 s8, v8
-; GFX10-NEXT: v_readfirstlane_b32 s9, v9
-; GFX10-NEXT: v_readfirstlane_b32 s10, v10
-; GFX10-NEXT: v_readfirstlane_b32 s11, v11
-; GFX10-NEXT: v_readfirstlane_b32 s12, v12
-; GFX10-NEXT: v_readfirstlane_b32 s13, v13
-; GFX10-NEXT: v_readfirstlane_b32 s14, v14
-; GFX10-NEXT: v_readfirstlane_b32 s15, v15
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_v16i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_nc_i32 v0, s0, s16 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v1, s1, s17 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v2, s2, s18 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v3, s3, s19 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v4, s4, s20 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v5, s5, s21 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v6, s6, s22 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v7, s7, s23 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v8, s8, s24 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v9, s9, s25 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v10, s10, s26 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v11, s11, s27 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v12, s12, s28 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v13, s13, s29 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v14, s14, s30 clamp
+; GFX10PLUS-NEXT: v_sub_nc_i32 v15, s15, s31 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v4
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s5, v5
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s6, v6
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s7, v7
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s8, v8
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s9, v9
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s10, v10
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s11, v11
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s12, v12
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s13, v13
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s14, v14
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s15, v15
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result
}
@@ -2507,12 +2654,12 @@ define i16 @v_ssubsat_i16(i16 %lhs, i16 %rhs) {
; GFX9-NEXT: v_sub_i16 v0, v0, v1 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_ssubsat_i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_sub_nc_i16 v0, v0, v1 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_sub_nc_i16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result
}
@@ -2556,11 +2703,11 @@ define amdgpu_ps i16 @s_ssubsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_ssubsat_i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_nc_i16 v0, s0, s1 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_nc_i16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result
}
@@ -2598,10 +2745,10 @@ define amdgpu_ps half @ssubsat_i16_sv(i16 inreg %lhs, i16 %rhs) {
; GFX9-NEXT: v_sub_i16 v0, s0, v0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: ssubsat_i16_sv:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_nc_i16 v0, s0, v0 clamp
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: ssubsat_i16_sv:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_nc_i16 v0, s0, v0 clamp
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)
%cast = bitcast i16 %result to half
ret half %cast
@@ -2638,10 +2785,10 @@ define amdgpu_ps half @ssubsat_i16_vs(i16 %lhs, i16 inreg %rhs) {
; GFX9-NEXT: v_sub_i16 v0, v0, s0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: ssubsat_i16_vs:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_nc_i16 v0, v0, s0 clamp
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: ssubsat_i16_vs:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_nc_i16 v0, v0, s0 clamp
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)
%cast = bitcast i16 %result to half
ret half %cast
@@ -2702,12 +2849,12 @@ define <2 x i16> @v_ssubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_ssubsat_v2i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_sub_i16 v0, v0, v1 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_v2i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_pk_sub_i16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
ret <2 x i16> %result
}
@@ -2783,11 +2930,11 @@ define amdgpu_ps i32 @s_ssubsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_ssubsat_v2i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_sub_i16 v0, s0, s1 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_v2i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_pk_sub_i16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to i32
ret i32 %cast
@@ -2852,10 +2999,10 @@ define amdgpu_ps float @ssubsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {
; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: ssubsat_v2i16_sv:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_sub_i16 v0, s0, v0 clamp
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: ssubsat_v2i16_sv:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_pk_sub_i16 v0, s0, v0 clamp
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to float
ret float %cast
@@ -2918,10 +3065,10 @@ define amdgpu_ps float @ssubsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
; GFX9-NEXT: v_pk_sub_i16 v0, v0, s0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: ssubsat_v2i16_vs:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_sub_i16 v0, v0, s0 clamp
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: ssubsat_v2i16_vs:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_pk_sub_i16 v0, v0, s0 clamp
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to float
ret float %cast
@@ -3040,13 +3187,13 @@ define <2 x float> @v_ssubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX9-NEXT: v_pk_sub_i16 v1, v1, v3 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_ssubsat_v4i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_sub_i16 v0, v0, v2 clamp
-; GFX10-NEXT: v_pk_sub_i16 v1, v1, v3 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_v4i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_pk_sub_i16 v0, v0, v2 clamp
+; GFX10PLUS-NEXT: v_pk_sub_i16 v1, v1, v3 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
%cast = bitcast <4 x i16> %result to <2 x float>
ret <2 x float> %cast
@@ -3180,13 +3327,13 @@ define amdgpu_ps <2 x i32> @s_ssubsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inre
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_ssubsat_v4i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_sub_i16 v0, s0, s2 clamp
-; GFX10-NEXT: v_pk_sub_i16 v1, s1, s3 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_v4i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_pk_sub_i16 v0, s0, s2 clamp
+; GFX10PLUS-NEXT: v_pk_sub_i16 v1, s1, s3 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
%cast = bitcast <4 x i16> %result to <2 x i32>
ret <2 x i32> %cast
@@ -3346,14 +3493,14 @@ define <3 x float> @v_ssubsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX9-NEXT: v_pk_sub_i16 v2, v2, v5 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_ssubsat_v6i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_sub_i16 v0, v0, v3 clamp
-; GFX10-NEXT: v_pk_sub_i16 v1, v1, v4 clamp
-; GFX10-NEXT: v_pk_sub_i16 v2, v2, v5 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_v6i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_pk_sub_i16 v0, v0, v3 clamp
+; GFX10PLUS-NEXT: v_pk_sub_i16 v1, v1, v4 clamp
+; GFX10PLUS-NEXT: v_pk_sub_i16 v2, v2, v5 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <6 x i16> @llvm.ssub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
%cast = bitcast <6 x i16> %result to <3 x float>
ret <3 x float> %cast
@@ -3544,15 +3691,15 @@ define amdgpu_ps <3 x i32> @s_ssubsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inre
; GFX9-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_ssubsat_v6i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_sub_i16 v0, s0, s3 clamp
-; GFX10-NEXT: v_pk_sub_i16 v1, s1, s4 clamp
-; GFX10-NEXT: v_pk_sub_i16 v2, s2, s5 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_v6i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_pk_sub_i16 v0, s0, s3 clamp
+; GFX10PLUS-NEXT: v_pk_sub_i16 v1, s1, s4 clamp
+; GFX10PLUS-NEXT: v_pk_sub_i16 v2, s2, s5 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <6 x i16> @llvm.ssub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
%cast = bitcast <6 x i16> %result to <3 x i32>
ret <3 x i32> %cast
@@ -3742,15 +3889,15 @@ define <4 x float> @v_ssubsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
; GFX9-NEXT: v_pk_sub_i16 v3, v3, v7 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_ssubsat_v8i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_sub_i16 v0, v0, v4 clamp
-; GFX10-NEXT: v_pk_sub_i16 v1, v1, v5 clamp
-; GFX10-NEXT: v_pk_sub_i16 v2, v2, v6 clamp
-; GFX10-NEXT: v_pk_sub_i16 v3, v3, v7 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_ssubsat_v8i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_pk_sub_i16 v0, v0, v4 clamp
+; GFX10PLUS-NEXT: v_pk_sub_i16 v1, v1, v5 clamp
+; GFX10PLUS-NEXT: v_pk_sub_i16 v2, v2, v6 clamp
+; GFX10PLUS-NEXT: v_pk_sub_i16 v3, v3, v7 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
%cast = bitcast <8 x i16> %result to <4 x float>
ret <4 x float> %cast
@@ -3998,17 +4145,17 @@ define amdgpu_ps <4 x i32> @s_ssubsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inre
; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_ssubsat_v8i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_sub_i16 v0, s0, s4 clamp
-; GFX10-NEXT: v_pk_sub_i16 v1, s1, s5 clamp
-; GFX10-NEXT: v_pk_sub_i16 v2, s2, s6 clamp
-; GFX10-NEXT: v_pk_sub_i16 v3, s3, s7 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_v8i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_pk_sub_i16 v0, s0, s4 clamp
+; GFX10PLUS-NEXT: v_pk_sub_i16 v1, s1, s5 clamp
+; GFX10PLUS-NEXT: v_pk_sub_i16 v2, s2, s6 clamp
+; GFX10PLUS-NEXT: v_pk_sub_i16 v3, s3, s7 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
%cast = bitcast <8 x i16> %result to <4 x i32>
ret <4 x i32> %cast
@@ -4103,6 +4250,22 @@ define i64 @v_ssubsat_i64(i64 %lhs, i64 %rhs) {
; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_ssubsat_i64:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v2
+; GFX11-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo
+; GFX11-NEXT: v_cmp_lt_i64_e64 s0, 0, v[2:3]
+; GFX11-NEXT: s_mov_b32 s1, 0
+; GFX11-NEXT: v_ashrrev_i32_e32 v6, 31, v5
+; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1]
+; GFX11-NEXT: v_add_co_ci_u32_e64 v1, s1, 0x80000000, v6, s1
+; GFX11-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
ret i64 %result
}
@@ -4177,24 +4340,24 @@ define amdgpu_ps i64 @s_ssubsat_i64(i64 inreg %lhs, i64 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_ssubsat_i64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_sub_u32 s4, s0, s2
-; GFX10-NEXT: s_subb_u32 s5, s1, s3
-; GFX10-NEXT: v_cmp_gt_i64_e64 s2, s[2:3], 0
-; GFX10-NEXT: v_cmp_lt_i64_e64 s1, s[4:5], s[0:1]
-; GFX10-NEXT: s_mov_b32 s3, 0
-; GFX10-NEXT: s_ashr_i32 s0, s5, 31
-; GFX10-NEXT: v_mov_b32_e32 v0, s4
-; GFX10-NEXT: v_mov_b32_e32 v1, s5
-; GFX10-NEXT: s_xor_b32 s2, s2, s1
-; GFX10-NEXT: s_cmp_lg_u32 s3, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s0, s2
-; GFX10-NEXT: s_addc_u32 s1, s0, 0x80000000
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s1, s2
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_i64:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_sub_u32 s4, s0, s2
+; GFX10PLUS-NEXT: s_subb_u32 s5, s1, s3
+; GFX10PLUS-NEXT: v_cmp_gt_i64_e64 s2, s[2:3], 0
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s1, s[4:5], s[0:1]
+; GFX10PLUS-NEXT: s_mov_b32 s3, 0
+; GFX10PLUS-NEXT: s_ashr_i32 s0, s5, 31
+; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s4
+; GFX10PLUS-NEXT: v_mov_b32_e32 v1, s5
+; GFX10PLUS-NEXT: s_xor_b32 s2, s2, s1
+; GFX10PLUS-NEXT: s_cmp_lg_u32 s3, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, s0, s2
+; GFX10PLUS-NEXT: s_addc_u32 s1, s0, 0x80000000
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s1, s2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
ret i64 %result
}
@@ -4248,19 +4411,19 @@ define amdgpu_ps <2 x float> @ssubsat_i64_sv(i64 inreg %lhs, i64 %rhs) {
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: ssubsat_i64_sv:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, s0, v0
-; GFX10-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v3
-; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_lt_i64_e64 s0, 0, v[0:1]
-; GFX10-NEXT: s_mov_b32 s1, 0
-; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s1, 0x80000000, v4, s1
-; GFX10-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: ssubsat_i64_sv:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_co_u32 v2, vcc_lo, s0, v0
+; GFX10PLUS-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v4, 31, v3
+; GFX10PLUS-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[2:3]
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s0, 0, v[0:1]
+; GFX10PLUS-NEXT: s_mov_b32 s1, 0
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e64 v1, s1, 0x80000000, v4, s1
+; GFX10PLUS-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
%cast = bitcast i64 %result to <2 x float>
ret <2 x float> %cast
@@ -4315,19 +4478,19 @@ define amdgpu_ps <2 x float> @ssubsat_i64_vs(i64 %lhs, i64 inreg %rhs) {
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: ssubsat_i64_vs:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v0, s0
-; GFX10-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT: v_cmp_gt_i64_e64 s1, s[0:1], 0
-; GFX10-NEXT: s_mov_b32 s0, 0
-; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v3
-; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]
-; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, 0x80000000, v4, s0
-; GFX10-NEXT: s_xor_b32 vcc_lo, s1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: ssubsat_i64_vs:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_co_u32 v2, vcc_lo, v0, s0
+; GFX10PLUS-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_gt_i64_e64 s1, s[0:1], 0
+; GFX10PLUS-NEXT: s_mov_b32 s0, 0
+; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v4, 31, v3
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e64 v1, s0, 0x80000000, v4, s0
+; GFX10PLUS-NEXT: s_xor_b32 vcc_lo, s1, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
%cast = bitcast i64 %result to <2 x float>
ret <2 x float> %cast
@@ -4433,6 +4596,31 @@ define <2 x i64> @v_ssubsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_ssubsat_v2i64:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_sub_co_u32 v8, vcc_lo, v0, v4
+; GFX11-NEXT: v_sub_co_ci_u32_e32 v9, vcc_lo, v1, v5, vcc_lo
+; GFX11-NEXT: v_sub_co_u32 v10, vcc_lo, v2, v6
+; GFX11-NEXT: v_sub_co_ci_u32_e32 v11, vcc_lo, v3, v7, vcc_lo
+; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[0:1]
+; GFX11-NEXT: v_ashrrev_i32_e32 v0, 31, v9
+; GFX11-NEXT: s_mov_b32 s1, 0
+; GFX11-NEXT: v_cmp_lt_i64_e64 s0, 0, v[4:5]
+; GFX11-NEXT: v_ashrrev_i32_e32 v4, 31, v11
+; GFX11-NEXT: v_cmp_lt_i64_e64 s3, 0, v[6:7]
+; GFX11-NEXT: v_add_co_ci_u32_e64 v1, s2, 0x80000000, v0, s1
+; GFX11-NEXT: v_cmp_lt_i64_e64 s2, v[10:11], v[2:3]
+; GFX11-NEXT: v_add_co_ci_u32_e64 v3, s1, 0x80000000, v4, s1
+; GFX11-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
+; GFX11-NEXT: s_xor_b32 vcc_lo, s3, s2
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v10, v4, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
ret <2 x i64> %result
}
@@ -4564,38 +4752,38 @@ define amdgpu_ps <2 x i64> @s_ssubsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inre
; GFX9-NEXT: v_readfirstlane_b32 s3, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_ssubsat_v2i64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_sub_u32 s8, s0, s4
-; GFX10-NEXT: s_subb_u32 s9, s1, s5
-; GFX10-NEXT: v_cmp_gt_i64_e64 s4, s[4:5], 0
-; GFX10-NEXT: v_cmp_lt_i64_e64 s1, s[8:9], s[0:1]
-; GFX10-NEXT: s_mov_b32 s10, 0
-; GFX10-NEXT: s_ashr_i32 s0, s9, 31
-; GFX10-NEXT: v_mov_b32_e32 v0, s8
-; GFX10-NEXT: v_mov_b32_e32 v1, s9
-; GFX10-NEXT: s_xor_b32 s8, s4, s1
-; GFX10-NEXT: s_cmp_lg_u32 s10, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s0, s8
-; GFX10-NEXT: s_addc_u32 s1, s0, 0x80000000
-; GFX10-NEXT: s_sub_u32 s4, s2, s6
-; GFX10-NEXT: s_subb_u32 s5, s3, s7
-; GFX10-NEXT: v_mov_b32_e32 v2, s4
-; GFX10-NEXT: v_cmp_lt_i64_e64 s2, s[4:5], s[2:3]
-; GFX10-NEXT: v_cmp_gt_i64_e64 s3, s[6:7], 0
-; GFX10-NEXT: s_ashr_i32 s0, s5, 31
-; GFX10-NEXT: v_mov_b32_e32 v3, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s1, s8
-; GFX10-NEXT: s_xor_b32 s2, s3, s2
-; GFX10-NEXT: s_cmp_lg_u32 s10, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s0, s2
-; GFX10-NEXT: s_addc_u32 s1, s0, 0x80000000
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s1, s2
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_v2i64:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_sub_u32 s8, s0, s4
+; GFX10PLUS-NEXT: s_subb_u32 s9, s1, s5
+; GFX10PLUS-NEXT: v_cmp_gt_i64_e64 s4, s[4:5], 0
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s1, s[8:9], s[0:1]
+; GFX10PLUS-NEXT: s_mov_b32 s10, 0
+; GFX10PLUS-NEXT: s_ashr_i32 s0, s9, 31
+; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s8
+; GFX10PLUS-NEXT: v_mov_b32_e32 v1, s9
+; GFX10PLUS-NEXT: s_xor_b32 s8, s4, s1
+; GFX10PLUS-NEXT: s_cmp_lg_u32 s10, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, s0, s8
+; GFX10PLUS-NEXT: s_addc_u32 s1, s0, 0x80000000
+; GFX10PLUS-NEXT: s_sub_u32 s4, s2, s6
+; GFX10PLUS-NEXT: s_subb_u32 s5, s3, s7
+; GFX10PLUS-NEXT: v_mov_b32_e32 v2, s4
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s2, s[4:5], s[2:3]
+; GFX10PLUS-NEXT: v_cmp_gt_i64_e64 s3, s[6:7], 0
+; GFX10PLUS-NEXT: s_ashr_i32 s0, s5, 31
+; GFX10PLUS-NEXT: v_mov_b32_e32 v3, s5
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s1, s8
+; GFX10PLUS-NEXT: s_xor_b32 s2, s3, s2
+; GFX10PLUS-NEXT: s_cmp_lg_u32 s10, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, v2, s0, s2
+; GFX10PLUS-NEXT: s_addc_u32 s1, s0, 0x80000000
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, v3, s1, s2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
ret <2 x i64> %result
}
@@ -4760,52 +4948,52 @@ define amdgpu_ps i128 @s_ssubsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_ssubsat_i128:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_sub_u32 s8, s0, s4
-; GFX10-NEXT: s_subb_u32 s9, s1, s5
-; GFX10-NEXT: s_subb_u32 s10, s2, s6
-; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[8:9], s[0:1]
-; GFX10-NEXT: s_subb_u32 s11, s3, s7
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], s[2:3]
-; GFX10-NEXT: s_cselect_b32 s12, 1, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[10:11], s[2:3]
-; GFX10-NEXT: v_cmp_gt_u64_e64 s2, s[4:5], 0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
-; GFX10-NEXT: s_and_b32 s0, 1, s12
-; GFX10-NEXT: s_cmp_eq_u64 s[6:7], 0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s2
-; GFX10-NEXT: v_cmp_gt_i64_e64 s2, s[6:7], 0
-; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT: s_cselect_b32 s1, 1, 0
-; GFX10-NEXT: s_ashr_i32 s0, s11, 31
-; GFX10-NEXT: s_and_b32 s1, 1, s1
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s2
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1
-; GFX10-NEXT: s_mov_b32 s1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s1, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
-; GFX10-NEXT: v_mov_b32_e32 v2, s9
-; GFX10-NEXT: v_mov_b32_e32 v3, s11
-; GFX10-NEXT: s_addc_u32 s1, s0, 0
-; GFX10-NEXT: s_addc_u32 s2, s0, 0
-; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
-; GFX10-NEXT: v_mov_b32_e32 v1, s8
-; GFX10-NEXT: s_addc_u32 s3, s0, 0x80000000
-; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_mov_b32_e32 v0, s10
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s3, vcc_lo
-; GFX10-NEXT: v_readfirstlane_b32 s0, v1
-; GFX10-NEXT: v_readfirstlane_b32 s1, v2
-; GFX10-NEXT: v_readfirstlane_b32 s2, v0
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_i128:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_sub_u32 s8, s0, s4
+; GFX10PLUS-NEXT: s_subb_u32 s9, s1, s5
+; GFX10PLUS-NEXT: s_subb_u32 s10, s2, s6
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s0, s[8:9], s[0:1]
+; GFX10PLUS-NEXT: s_subb_u32 s11, s3, s7
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[10:11], s[2:3]
+; GFX10PLUS-NEXT: s_cselect_b32 s12, 1, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s0, s[10:11], s[2:3]
+; GFX10PLUS-NEXT: v_cmp_gt_u64_e64 s2, s[4:5], 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX10PLUS-NEXT: s_and_b32 s0, 1, s12
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[6:7], 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, 0, 1, s2
+; GFX10PLUS-NEXT: v_cmp_gt_i64_e64 s2, s[6:7], 0
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
+; GFX10PLUS-NEXT: s_cselect_b32 s1, 1, 0
+; GFX10PLUS-NEXT: s_ashr_i32 s0, s11, 31
+; GFX10PLUS-NEXT: s_and_b32 s1, 1, s1
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, 0, 1, s2
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1
+; GFX10PLUS-NEXT: s_mov_b32 s1, 0
+; GFX10PLUS-NEXT: s_cmp_lg_u32 s1, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
+; GFX10PLUS-NEXT: v_mov_b32_e32 v2, s9
+; GFX10PLUS-NEXT: v_mov_b32_e32 v3, s11
+; GFX10PLUS-NEXT: s_addc_u32 s1, s0, 0
+; GFX10PLUS-NEXT: s_addc_u32 s2, s0, 0
+; GFX10PLUS-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX10PLUS-NEXT: v_mov_b32_e32 v1, s8
+; GFX10PLUS-NEXT: s_addc_u32 s3, s0, 0x80000000
+; GFX10PLUS-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s10
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s0, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, v2, s1, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, v3, s3, vcc_lo
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i128 @llvm.ssub.sat.i128(i128 %lhs, i128 %rhs)
ret i128 %result
}
@@ -4919,37 +5107,37 @@ define amdgpu_ps <4 x float> @ssubsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: ssubsat_i128_sv:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, s0, v0
-; GFX10-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT: v_sub_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
-; GFX10-NEXT: v_sub_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
-; GFX10-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[4:5]
-; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[6:7]
-; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, 0, v[0:1]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[6:7]
-; GFX10-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v7
-; GFX10-NEXT: s_mov_b32 vcc_lo, 0
-; GFX10-NEXT: v_xor_b32_e32 v0, v0, v8
-; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v1, vcc_lo
-; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
-; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0x80000000, v1, vcc_lo
-; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v1, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v2, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v3, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v8, s0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: ssubsat_i128_sv:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_co_u32 v4, vcc_lo, s0, v0
+; GFX10PLUS-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT: v_sub_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
+; GFX10PLUS-NEXT: v_sub_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[4:5]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[6:7]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e32 vcc_lo, 0, v[0:1]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[6:7]
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v1, 31, v7
+; GFX10PLUS-NEXT: s_mov_b32 vcc_lo, 0
+; GFX10PLUS-NEXT: v_xor_b32_e32 v0, v0, v8
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v1, vcc_lo
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
+; GFX10PLUS-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0x80000000, v1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v4, v1, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v5, v2, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, v6, v3, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, v7, v8, s0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i128 @llvm.ssub.sat.i128(i128 %lhs, i128 %rhs)
%cast = bitcast i128 %result to <4 x float>
ret <4 x float> %cast
@@ -5070,40 +5258,40 @@ define amdgpu_ps <4 x float> @ssubsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: ssubsat_i128_vs:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v0, s0
-; GFX10-NEXT: v_subrev_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT: v_subrev_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
-; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
-; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[0:1]
-; GFX10-NEXT: v_cmp_gt_u64_e64 s0, s[0:1], 0
-; GFX10-NEXT: s_cmp_eq_u64 s[2:3], 0
-; GFX10-NEXT: s_cselect_b32 s4, 1, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
-; GFX10-NEXT: v_cmp_gt_i64_e64 s0, s[2:3], 0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
-; GFX10-NEXT: s_and_b32 s0, 1, s4
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc_lo
-; GFX10-NEXT: s_mov_b32 vcc_lo, 0
-; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
-; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v7
-; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v1, vcc_lo
-; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
-; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
-; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0x80000000, v1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v1, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v2, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v3, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v8, s0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: ssubsat_i128_vs:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_co_u32 v4, vcc_lo, v0, s0
+; GFX10PLUS-NEXT: v_subrev_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT: v_subrev_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
+; GFX10PLUS-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[0:1]
+; GFX10PLUS-NEXT: v_cmp_gt_u64_e64 s0, s[0:1], 0
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[2:3], 0
+; GFX10PLUS-NEXT: s_cselect_b32 s4, 1, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[2:3]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
+; GFX10PLUS-NEXT: v_cmp_gt_i64_e64 s0, s[2:3], 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
+; GFX10PLUS-NEXT: s_and_b32 s0, 1, s4
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc_lo
+; GFX10PLUS-NEXT: s_mov_b32 vcc_lo, 0
+; GFX10PLUS-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v1, 31, v7
+; GFX10PLUS-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v1, vcc_lo
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0x80000000, v1, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v4, v1, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v5, v2, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, v6, v3, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, v7, v8, s0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i128 @llvm.ssub.sat.i128(i128 %lhs, i128 %rhs)
%cast = bitcast i128 %result to <4 x float>
ret <4 x float> %cast
@@ -5353,6 +5541,67 @@ define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX10-NEXT: v_cndmask_b32_e64 v6, v10, v12, s4
; GFX10-NEXT: v_cndmask_b32_e64 v7, v11, v13, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_ssubsat_v2i128:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_sub_co_u32 v16, vcc_lo, v0, v8
+; GFX11-NEXT: v_sub_co_ci_u32_e32 v17, vcc_lo, v1, v9, vcc_lo
+; GFX11-NEXT: v_sub_co_ci_u32_e32 v18, vcc_lo, v2, v10, vcc_lo
+; GFX11-NEXT: v_sub_co_ci_u32_e32 v19, vcc_lo, v3, v11, vcc_lo
+; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[16:17], v[0:1]
+; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[18:19], v[2:3]
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, 0, v[8:9]
+; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[2:3]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc_lo
+; GFX11-NEXT: v_sub_co_u32 v8, vcc_lo, v4, v12
+; GFX11-NEXT: v_sub_co_ci_u32_e32 v9, vcc_lo, v5, v13, vcc_lo
+; GFX11-NEXT: v_sub_co_ci_u32_e32 v10, vcc_lo, v6, v14, vcc_lo
+; GFX11-NEXT: v_sub_co_ci_u32_e32 v11, vcc_lo, v7, v15, vcc_lo
+; GFX11-NEXT: v_cmp_lt_u64_e64 s1, v[8:9], v[4:5]
+; GFX11-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX11-NEXT: v_ashrrev_i32_e32 v1, 31, v19
+; GFX11-NEXT: v_cmp_eq_u64_e64 s2, v[10:11], v[6:7]
+; GFX11-NEXT: s_mov_b32 vcc_lo, 0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, s1
+; GFX11-NEXT: v_cmp_lt_i64_e64 s1, v[10:11], v[6:7]
+; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-NEXT: v_ashrrev_i32_e32 v6, 31, v11
+; GFX11-NEXT: v_add_co_ci_u32_e64 v2, s0, 0, v1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, s1
+; GFX11-NEXT: v_cmp_lt_u64_e64 s1, 0, v[12:13]
+; GFX11-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v6, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 1, s1
+; GFX11-NEXT: v_cmp_lt_i64_e64 s1, 0, v[14:15]
+; GFX11-NEXT: v_cndmask_b32_e64 v12, 0, 1, s1
+; GFX11-NEXT: v_cmp_ne_u32_e64 s1, 0, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, v3, s2
+; GFX11-NEXT: v_cmp_eq_u64_e64 s2, 0, v[14:15]
+; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s0, 0, v1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v12, v5, s2
+; GFX11-NEXT: v_add_co_ci_u32_e32 v12, vcc_lo, 0, v6, vcc_lo
+; GFX11-NEXT: v_add_co_ci_u32_e64 v5, s0, 0x80000000, v1, s0
+; GFX11-NEXT: v_xor_b32_e32 v3, v3, v0
+; GFX11-NEXT: v_add_co_ci_u32_e32 v13, vcc_lo, 0x80000000, v6, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v16, v1, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v17, v2, s1
+; GFX11-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v18, v4, s1
+; GFX11-NEXT: v_cmp_ne_u32_e64 s0, 0, v3
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v19, v5, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v8, v6, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v9, v7, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v10, v12, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v11, v13, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
ret <2 x i128> %result
}
@@ -5664,94 +5913,94 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX9-NEXT: v_readfirstlane_b32 s7, v3
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_ssubsat_v2i128:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_sub_u32 s16, s0, s8
-; GFX10-NEXT: s_subb_u32 s17, s1, s9
-; GFX10-NEXT: s_subb_u32 s18, s2, s10
-; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[16:17], s[0:1]
-; GFX10-NEXT: s_subb_u32 s19, s3, s11
-; GFX10-NEXT: s_cmp_eq_u64 s[18:19], s[2:3]
-; GFX10-NEXT: s_cselect_b32 s20, 1, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[18:19], s[2:3]
-; GFX10-NEXT: v_cmp_gt_u64_e64 s2, s[8:9], 0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
-; GFX10-NEXT: s_and_b32 s0, 1, s20
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s2
-; GFX10-NEXT: s_cselect_b32 s1, 1, 0
-; GFX10-NEXT: v_cmp_gt_i64_e64 s2, s[10:11], 0
-; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT: s_mov_b32 s20, 0
-; GFX10-NEXT: s_and_b32 s1, 1, s1
-; GFX10-NEXT: s_ashr_i32 s0, s19, 31
-; GFX10-NEXT: s_cmp_lg_u32 s20, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1
-; GFX10-NEXT: s_addc_u32 s1, s0, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s2
-; GFX10-NEXT: s_addc_u32 s2, s0, 0
-; GFX10-NEXT: s_addc_u32 s3, s0, 0x80000000
-; GFX10-NEXT: s_sub_u32 s8, s4, s12
-; GFX10-NEXT: s_subb_u32 s9, s5, s13
-; GFX10-NEXT: s_subb_u32 s10, s6, s14
-; GFX10-NEXT: v_cmp_lt_u64_e64 s4, s[8:9], s[4:5]
-; GFX10-NEXT: s_subb_u32 s11, s7, s15
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
-; GFX10-NEXT: s_cmp_eq_u64 s[10:11], s[6:7]
-; GFX10-NEXT: v_mov_b32_e32 v2, s17
-; GFX10-NEXT: v_mov_b32_e32 v7, s11
-; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
-; GFX10-NEXT: v_cmp_lt_i64_e64 s4, s[10:11], s[6:7]
-; GFX10-NEXT: v_cmp_gt_u64_e64 s6, s[12:13], 0
-; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
-; GFX10-NEXT: v_mov_b32_e32 v1, s16
-; GFX10-NEXT: s_cselect_b32 s16, 1, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4
-; GFX10-NEXT: s_and_b32 s4, 1, s16
-; GFX10-NEXT: s_cmp_eq_u64 s[14:15], 0
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s6
-; GFX10-NEXT: v_cmp_gt_i64_e64 s6, s[14:15], 0
-; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4
-; GFX10-NEXT: s_cselect_b32 s5, 1, 0
-; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT: s_and_b32 s5, 1, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s6
-; GFX10-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
-; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc_lo
-; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_mov_b32_e32 v0, s18
-; GFX10-NEXT: v_mov_b32_e32 v5, s19
-; GFX10-NEXT: v_mov_b32_e32 v6, s9
-; GFX10-NEXT: v_xor_b32_e32 v3, v4, v3
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s0, vcc_lo
-; GFX10-NEXT: s_ashr_i32 s0, s11, 31
-; GFX10-NEXT: s_cmp_lg_u32 s20, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s1, vcc_lo
-; GFX10-NEXT: v_and_b32_e32 v3, 1, v3
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v5, s3, vcc_lo
-; GFX10-NEXT: v_mov_b32_e32 v5, s8
-; GFX10-NEXT: s_addc_u32 s1, s0, 0
-; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
-; GFX10-NEXT: v_mov_b32_e32 v3, s10
-; GFX10-NEXT: s_addc_u32 s2, s0, 0
-; GFX10-NEXT: s_addc_u32 s3, s0, 0x80000000
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, s1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s2, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, s3, vcc_lo
-; GFX10-NEXT: v_readfirstlane_b32 s0, v1
-; GFX10-NEXT: v_readfirstlane_b32 s1, v2
-; GFX10-NEXT: v_readfirstlane_b32 s2, v0
-; GFX10-NEXT: v_readfirstlane_b32 s3, v4
-; GFX10-NEXT: v_readfirstlane_b32 s4, v5
-; GFX10-NEXT: v_readfirstlane_b32 s5, v6
-; GFX10-NEXT: v_readfirstlane_b32 s6, v3
-; GFX10-NEXT: v_readfirstlane_b32 s7, v7
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_ssubsat_v2i128:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_sub_u32 s16, s0, s8
+; GFX10PLUS-NEXT: s_subb_u32 s17, s1, s9
+; GFX10PLUS-NEXT: s_subb_u32 s18, s2, s10
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s0, s[16:17], s[0:1]
+; GFX10PLUS-NEXT: s_subb_u32 s19, s3, s11
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[18:19], s[2:3]
+; GFX10PLUS-NEXT: s_cselect_b32 s20, 1, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s0, s[18:19], s[2:3]
+; GFX10PLUS-NEXT: v_cmp_gt_u64_e64 s2, s[8:9], 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX10PLUS-NEXT: s_and_b32 s0, 1, s20
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, 0, 1, s2
+; GFX10PLUS-NEXT: s_cselect_b32 s1, 1, 0
+; GFX10PLUS-NEXT: v_cmp_gt_i64_e64 s2, s[10:11], 0
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
+; GFX10PLUS-NEXT: s_mov_b32 s20, 0
+; GFX10PLUS-NEXT: s_and_b32 s1, 1, s1
+; GFX10PLUS-NEXT: s_ashr_i32 s0, s19, 31
+; GFX10PLUS-NEXT: s_cmp_lg_u32 s20, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1
+; GFX10PLUS-NEXT: s_addc_u32 s1, s0, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, 0, 1, s2
+; GFX10PLUS-NEXT: s_addc_u32 s2, s0, 0
+; GFX10PLUS-NEXT: s_addc_u32 s3, s0, 0x80000000
+; GFX10PLUS-NEXT: s_sub_u32 s8, s4, s12
+; GFX10PLUS-NEXT: s_subb_u32 s9, s5, s13
+; GFX10PLUS-NEXT: s_subb_u32 s10, s6, s14
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s4, s[8:9], s[4:5]
+; GFX10PLUS-NEXT: s_subb_u32 s11, s7, s15
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[10:11], s[6:7]
+; GFX10PLUS-NEXT: v_mov_b32_e32 v2, s17
+; GFX10PLUS-NEXT: v_mov_b32_e32 v7, s11
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s4, s[10:11], s[6:7]
+; GFX10PLUS-NEXT: v_cmp_gt_u64_e64 s6, s[12:13], 0
+; GFX10PLUS-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX10PLUS-NEXT: v_mov_b32_e32 v1, s16
+; GFX10PLUS-NEXT: s_cselect_b32 s16, 1, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4
+; GFX10PLUS-NEXT: s_and_b32 s4, 1, s16
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[14:15], 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v5, 0, 1, s6
+; GFX10PLUS-NEXT: v_cmp_gt_i64_e64 s6, s[14:15], 0
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4
+; GFX10PLUS-NEXT: s_cselect_b32 s5, 1, 0
+; GFX10PLUS-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10PLUS-NEXT: s_and_b32 s5, 1, s5
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v6, 0, 1, s6
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s18
+; GFX10PLUS-NEXT: v_mov_b32_e32 v5, s19
+; GFX10PLUS-NEXT: v_mov_b32_e32 v6, s9
+; GFX10PLUS-NEXT: v_xor_b32_e32 v3, v4, v3
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s0, vcc_lo
+; GFX10PLUS-NEXT: s_ashr_i32 s0, s11, 31
+; GFX10PLUS-NEXT: s_cmp_lg_u32 s20, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, v2, s1, vcc_lo
+; GFX10PLUS-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v4, v5, s3, vcc_lo
+; GFX10PLUS-NEXT: v_mov_b32_e32 v5, s8
+; GFX10PLUS-NEXT: s_addc_u32 s1, s0, 0
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
+; GFX10PLUS-NEXT: v_mov_b32_e32 v3, s10
+; GFX10PLUS-NEXT: s_addc_u32 s2, s0, 0
+; GFX10PLUS-NEXT: s_addc_u32 s3, s0, 0x80000000
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v5, v5, s0, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v6, v6, s1, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, v3, s2, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v7, v7, s3, vcc_lo
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v4
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v5
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s5, v6
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s6, v3
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s7, v7
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
ret <2 x i128> %result
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
index 16de70970ce7a..6682204beccb3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
@@ -2,7 +2,8 @@
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -o - %s | FileCheck -check-prefix=GFX6 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s | FileCheck -check-prefix=GFX8 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
define i7 @v_uaddsat_i7(i7 %lhs, i7 %rhs) {
; GFX6-LABEL: v_uaddsat_i7:
@@ -34,15 +35,15 @@ define i7 @v_uaddsat_i7(i7 %lhs, i7 %rhs) {
; GFX9-NEXT: v_lshrrev_b16_e32 v0, 9, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_uaddsat_i7:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_lshlrev_b16 v0, 9, v0
-; GFX10-NEXT: v_lshlrev_b16 v1, 9, v1
-; GFX10-NEXT: v_add_nc_u16 v0, v0, v1 clamp
-; GFX10-NEXT: v_lshrrev_b16 v0, 9, v0
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_i7:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_lshlrev_b16 v0, 9, v0
+; GFX10PLUS-NEXT: v_lshlrev_b16 v1, 9, v1
+; GFX10PLUS-NEXT: v_add_nc_u16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT: v_lshrrev_b16 v0, 9, v0
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call i7 @llvm.uadd.sat.i7(i7 %lhs, i7 %rhs)
ret i7 %result
}
@@ -80,15 +81,15 @@ define amdgpu_ps i7 @s_uaddsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_uaddsat_i7:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_bfe_u32 s2, 9, 0x100000
-; GFX10-NEXT: s_lshl_b32 s0, s0, s2
-; GFX10-NEXT: s_lshl_b32 s1, s1, s2
-; GFX10-NEXT: v_add_nc_u16 v0, s0, s1 clamp
-; GFX10-NEXT: v_lshrrev_b16 v0, 9, v0
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_i7:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_bfe_u32 s2, 9, 0x100000
+; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, s2
+; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, s2
+; GFX10PLUS-NEXT: v_add_nc_u16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT: v_lshrrev_b16 v0, 9, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i7 @llvm.uadd.sat.i7(i7 %lhs, i7 %rhs)
ret i7 %result
}
@@ -123,15 +124,15 @@ define i8 @v_uaddsat_i8(i8 %lhs, i8 %rhs) {
; GFX9-NEXT: v_lshrrev_b16_e32 v0, 8, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_uaddsat_i8:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_lshlrev_b16 v0, 8, v0
-; GFX10-NEXT: v_lshlrev_b16 v1, 8, v1
-; GFX10-NEXT: v_add_nc_u16 v0, v0, v1 clamp
-; GFX10-NEXT: v_lshrrev_b16 v0, 8, v0
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_i8:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_lshlrev_b16 v0, 8, v0
+; GFX10PLUS-NEXT: v_lshlrev_b16 v1, 8, v1
+; GFX10PLUS-NEXT: v_add_nc_u16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT: v_lshrrev_b16 v0, 8, v0
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call i8 @llvm.uadd.sat.i8(i8 %lhs, i8 %rhs)
ret i8 %result
}
@@ -169,15 +170,15 @@ define amdgpu_ps i8 @s_uaddsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_uaddsat_i8:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_bfe_u32 s2, 8, 0x100000
-; GFX10-NEXT: s_lshl_b32 s0, s0, s2
-; GFX10-NEXT: s_lshl_b32 s1, s1, s2
-; GFX10-NEXT: v_add_nc_u16 v0, s0, s1 clamp
-; GFX10-NEXT: v_lshrrev_b16 v0, 8, v0
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_i8:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_bfe_u32 s2, 8, 0x100000
+; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, s2
+; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, s2
+; GFX10PLUS-NEXT: v_add_nc_u16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT: v_lshrrev_b16 v0, 8, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i8 @llvm.uadd.sat.i8(i8 %lhs, i8 %rhs)
ret i8 %result
}
@@ -254,6 +255,27 @@ define i16 @v_uaddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX10-NEXT: v_and_b32_sdwa v1, v0, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_uaddsat_v2i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_lshrrev_b32_e32 v2, 8, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT: v_and_or_b32 v0, 0xffff, v0, v2
+; GFX11-NEXT: v_and_or_b32 v1, 0xffff, v1, v3
+; GFX11-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_u16 v0, v0, v1 clamp
+; GFX11-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8>
%result = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
@@ -345,6 +367,30 @@ define amdgpu_ps i16 @s_uaddsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_uaddsat_v2i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshr_b32 s2, s0, 8
+; GFX11-NEXT: s_lshr_b32 s3, s1, 8
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s2
+; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s3
+; GFX11-NEXT: s_lshr_b32 s2, s0, 16
+; GFX11-NEXT: s_lshr_b32 s3, s1, 16
+; GFX11-NEXT: s_lshl_b32 s0, s0, 0x80008
+; GFX11-NEXT: s_lshl_b32 s2, s2, 8
+; GFX11-NEXT: s_lshl_b32 s1, s1, 0x80008
+; GFX11-NEXT: s_lshl_b32 s3, s3, 8
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s2
+; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s3
+; GFX11-NEXT: v_pk_add_u16 v0, s0, s1 clamp
+; GFX11-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: ; return to shader part epilog
%lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8>
%result = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
@@ -493,6 +539,42 @@ define i32 @v_uaddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX10-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_uaddsat_v4i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_lshrrev_b32_e32 v2, 8, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v5, 24, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v6, 24, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-NEXT: v_and_or_b32 v0, 0xffff, v0, v2
+; GFX11-NEXT: v_and_or_b32 v1, 0xffff, v1, v3
+; GFX11-NEXT: v_and_or_b32 v2, 0xffff, v4, v5
+; GFX11-NEXT: v_and_or_b32 v3, 0xffff, v7, v6
+; GFX11-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_u16 v0, v0, v1 clamp
+; GFX11-NEXT: v_pk_add_u16 v1, v2, v3 clamp
+; GFX11-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT: v_bfe_u32 v2, v0, 16, 8
+; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v1
+; GFX11-NEXT: v_bfe_u32 v1, v1, 16, 8
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; GFX11-NEXT: v_and_or_b32 v0, v0, 0xff, v2
+; GFX11-NEXT: v_or3_b32 v0, v0, v3, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8>
%result = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
@@ -666,6 +748,47 @@ define amdgpu_ps i32 @s_uaddsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) {
; GFX10-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_uaddsat_v4i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshr_b32 s2, s0, 8
+; GFX11-NEXT: s_lshr_b32 s4, s1, 8
+; GFX11-NEXT: s_pack_ll_b32_b16 s2, s0, s2
+; GFX11-NEXT: s_pack_ll_b32_b16 s4, s1, s4
+; GFX11-NEXT: s_lshr_b32 s6, s2, 16
+; GFX11-NEXT: s_lshl_b32 s2, s2, 0x80008
+; GFX11-NEXT: s_lshl_b32 s6, s6, 8
+; GFX11-NEXT: s_lshr_b32 s3, s0, 24
+; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s6
+; GFX11-NEXT: s_lshr_b32 s6, s4, 16
+; GFX11-NEXT: s_lshr_b32 s5, s1, 24
+; GFX11-NEXT: s_lshl_b32 s4, s4, 0x80008
+; GFX11-NEXT: s_lshl_b32 s6, s6, 8
+; GFX11-NEXT: s_pack_hl_b32_b16 s0, s0, s3
+; GFX11-NEXT: s_pack_hl_b32_b16 s1, s1, s5
+; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s6
+; GFX11-NEXT: s_lshr_b32 s3, s0, 16
+; GFX11-NEXT: s_lshr_b32 s5, s1, 16
+; GFX11-NEXT: v_pk_add_u16 v0, s2, s4 clamp
+; GFX11-NEXT: s_lshl_b32 s0, s0, 0x80008
+; GFX11-NEXT: s_lshl_b32 s3, s3, 8
+; GFX11-NEXT: s_lshl_b32 s1, s1, 0x80008
+; GFX11-NEXT: s_lshl_b32 s2, s5, 8
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s3
+; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s2
+; GFX11-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_u16 v1, s0, s1 clamp
+; GFX11-NEXT: v_bfe_u32 v2, v0, 16, 8
+; GFX11-NEXT: v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v1
+; GFX11-NEXT: v_bfe_u32 v1, v1, 16, 8
+; GFX11-NEXT: v_and_or_b32 v0, v0, 0xff, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; GFX11-NEXT: v_or3_b32 v0, v0, v2, v1
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: ; return to shader part epilog
%lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8>
%result = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
@@ -703,15 +826,15 @@ define i24 @v_uaddsat_i24(i24 %lhs, i24 %rhs) {
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 8, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_uaddsat_i24:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v1 clamp
-; GFX10-NEXT: v_lshrrev_b32_e32 v0, 8, v0
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_i24:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v0, v0, v1 clamp
+; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, 8, v0
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call i24 @llvm.uadd.sat.i24(i24 %lhs, i24 %rhs)
ret i24 %result
}
@@ -747,14 +870,14 @@ define amdgpu_ps i24 @s_uaddsat_i24(i24 inreg %lhs, i24 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_uaddsat_i24:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_lshl_b32 s0, s0, 8
-; GFX10-NEXT: s_lshl_b32 s1, s1, 8
-; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, s1 clamp
-; GFX10-NEXT: v_lshrrev_b32_e32 v0, 8, v0
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_i24:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, 8
+; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, 8
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v0, s0, s1 clamp
+; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, 8, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i24 @llvm.uadd.sat.i24(i24 %lhs, i24 %rhs)
ret i24 %result
}
@@ -780,12 +903,12 @@ define i32 @v_uaddsat_i32(i32 %lhs, i32 %rhs) {
; GFX9-NEXT: v_add_u32_e64 v0, v0, v1 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_uaddsat_i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v1 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v0, v0, v1 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs)
ret i32 %result
}
@@ -812,11 +935,11 @@ define amdgpu_ps i32 @s_uaddsat_i32(i32 inreg %lhs, i32 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_uaddsat_i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, s1 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v0, s0, s1 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs)
ret i32 %result
}
@@ -839,10 +962,10 @@ define amdgpu_ps float @uaddsat_i32_sv(i32 inreg %lhs, i32 %rhs) {
; GFX9-NEXT: v_add_u32_e64 v0, s0, v0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: uaddsat_i32_sv:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, v0 clamp
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: uaddsat_i32_sv:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v0, s0, v0 clamp
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs)
%cast = bitcast i32 %result to float
ret float %cast
@@ -866,10 +989,10 @@ define amdgpu_ps float @uaddsat_i32_vs(i32 %lhs, i32 inreg %rhs) {
; GFX9-NEXT: v_add_u32_e64 v0, v0, s0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: uaddsat_i32_vs:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, s0 clamp
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: uaddsat_i32_vs:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v0, v0, s0 clamp
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs)
%cast = bitcast i32 %result to float
ret float %cast
@@ -901,13 +1024,13 @@ define <2 x i32> @v_uaddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
; GFX9-NEXT: v_add_u32_e64 v1, v1, v3 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_uaddsat_v2i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v2 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v1, v1, v3 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_v2i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v0, v0, v2 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v1, v1, v3 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
ret <2 x i32> %result
}
@@ -943,13 +1066,13 @@ define amdgpu_ps <2 x i32> @s_uaddsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inre
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_uaddsat_v2i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, s2 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v1, s1, s3 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_v2i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v0, s0, s2 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v1, s1, s3 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
ret <2 x i32> %result
}
@@ -985,14 +1108,14 @@ define <3 x i32> @v_uaddsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
; GFX9-NEXT: v_add_u32_e64 v2, v2, v5 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_uaddsat_v3i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v3 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v1, v1, v4 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, v5 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_v3i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v0, v0, v3 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v1, v1, v4 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v2, v2, v5 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x i32> @llvm.uadd.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
ret <3 x i32> %result
}
@@ -1037,15 +1160,15 @@ define amdgpu_ps <3 x i32> @s_uaddsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inre
; GFX9-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_uaddsat_v3i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, s3 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v1, s1, s4 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v2, s2, s5 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_v3i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v0, s0, s3 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v1, s1, s4 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v2, s2, s5 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <3 x i32> @llvm.uadd.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
ret <3 x i32> %result
}
@@ -1086,15 +1209,15 @@ define <4 x i32> @v_uaddsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; GFX9-NEXT: v_add_u32_e64 v3, v3, v7 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_uaddsat_v4i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v4 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v1, v1, v5 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, v6 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v3, v3, v7 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_v4i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v0, v0, v4 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v1, v1, v5 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v2, v2, v6 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v3, v3, v7 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
ret <4 x i32> %result
}
@@ -1148,17 +1271,17 @@ define amdgpu_ps <4 x i32> @s_uaddsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inre
; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_uaddsat_v4i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, s4 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v1, s1, s5 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v2, s2, s6 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v3, s3, s7 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_v4i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v0, s0, s4 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v1, s1, s5 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v2, s2, s6 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v3, s3, s7 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
ret <4 x i32> %result
}
@@ -1204,16 +1327,16 @@ define <5 x i32> @v_uaddsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
; GFX9-NEXT: v_add_u32_e64 v4, v4, v9 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_uaddsat_v5i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v5 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v1, v1, v6 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, v7 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v3, v3, v8 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v4, v4, v9 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_v5i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v0, v0, v5 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v1, v1, v6 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v2, v2, v7 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v3, v3, v8 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v4, v4, v9 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <5 x i32> @llvm.uadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
ret <5 x i32> %result
}
@@ -1276,19 +1399,19 @@ define amdgpu_ps <5 x i32> @s_uaddsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inre
; GFX9-NEXT: v_readfirstlane_b32 s4, v4
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_uaddsat_v5i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, s5 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v1, s1, s6 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v2, s2, s7 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v3, s3, s8 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v4, s4, s9 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: v_readfirstlane_b32 s4, v4
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_v5i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v0, s0, s5 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v1, s1, s6 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v2, s2, s7 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v3, s3, s8 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v4, s4, s9 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v4
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <5 x i32> @llvm.uadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
ret <5 x i32> %result
}
@@ -1418,6 +1541,30 @@ define <16 x i32> @v_uaddsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_nc_u32_e64 v15, v15, v31 clamp
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_uaddsat_v16i32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_b32 v31, off, s32
+; GFX11-NEXT: v_add_nc_u32_e64 v0, v0, v16 clamp
+; GFX11-NEXT: v_add_nc_u32_e64 v1, v1, v17 clamp
+; GFX11-NEXT: v_add_nc_u32_e64 v2, v2, v18 clamp
+; GFX11-NEXT: v_add_nc_u32_e64 v3, v3, v19 clamp
+; GFX11-NEXT: v_add_nc_u32_e64 v4, v4, v20 clamp
+; GFX11-NEXT: v_add_nc_u32_e64 v5, v5, v21 clamp
+; GFX11-NEXT: v_add_nc_u32_e64 v6, v6, v22 clamp
+; GFX11-NEXT: v_add_nc_u32_e64 v7, v7, v23 clamp
+; GFX11-NEXT: v_add_nc_u32_e64 v8, v8, v24 clamp
+; GFX11-NEXT: v_add_nc_u32_e64 v9, v9, v25 clamp
+; GFX11-NEXT: v_add_nc_u32_e64 v10, v10, v26 clamp
+; GFX11-NEXT: v_add_nc_u32_e64 v11, v11, v27 clamp
+; GFX11-NEXT: v_add_nc_u32_e64 v12, v12, v28 clamp
+; GFX11-NEXT: v_add_nc_u32_e64 v13, v13, v29 clamp
+; GFX11-NEXT: v_add_nc_u32_e64 v14, v14, v30 clamp
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_add_nc_u32_e64 v15, v15, v31 clamp
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result
}
@@ -1579,41 +1726,41 @@ define amdgpu_ps <16 x i32> @s_uaddsat_v16i32(<16 x i32> inreg %lhs, <16 x i32>
; GFX9-NEXT: v_readfirstlane_b32 s15, v15
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_uaddsat_v16i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, s16 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v1, s1, s17 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v2, s2, s18 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v3, s3, s19 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v4, s4, s20 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v5, s5, s21 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v6, s6, s22 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v7, s7, s23 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v8, s8, s24 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v9, s9, s25 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v10, s10, s26 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v11, s11, s27 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v12, s12, s28 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v13, s13, s29 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v14, s14, s30 clamp
-; GFX10-NEXT: v_add_nc_u32_e64 v15, s15, s31 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: v_readfirstlane_b32 s4, v4
-; GFX10-NEXT: v_readfirstlane_b32 s5, v5
-; GFX10-NEXT: v_readfirstlane_b32 s6, v6
-; GFX10-NEXT: v_readfirstlane_b32 s7, v7
-; GFX10-NEXT: v_readfirstlane_b32 s8, v8
-; GFX10-NEXT: v_readfirstlane_b32 s9, v9
-; GFX10-NEXT: v_readfirstlane_b32 s10, v10
-; GFX10-NEXT: v_readfirstlane_b32 s11, v11
-; GFX10-NEXT: v_readfirstlane_b32 s12, v12
-; GFX10-NEXT: v_readfirstlane_b32 s13, v13
-; GFX10-NEXT: v_readfirstlane_b32 s14, v14
-; GFX10-NEXT: v_readfirstlane_b32 s15, v15
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_v16i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v0, s0, s16 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v1, s1, s17 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v2, s2, s18 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v3, s3, s19 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v4, s4, s20 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v5, s5, s21 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v6, s6, s22 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v7, s7, s23 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v8, s8, s24 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v9, s9, s25 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v10, s10, s26 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v11, s11, s27 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v12, s12, s28 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v13, s13, s29 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v14, s14, s30 clamp
+; GFX10PLUS-NEXT: v_add_nc_u32_e64 v15, s15, s31 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v4
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s5, v5
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s6, v6
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s7, v7
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s8, v8
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s9, v9
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s10, v10
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s11, v11
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s12, v12
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s13, v13
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s14, v14
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s15, v15
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result
}
@@ -1642,12 +1789,12 @@ define i16 @v_uaddsat_i16(i16 %lhs, i16 %rhs) {
; GFX9-NEXT: v_add_u16_e64 v0, v0, v1 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_uaddsat_i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_add_nc_u16 v0, v0, v1 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_add_nc_u16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result
}
@@ -1677,11 +1824,11 @@ define amdgpu_ps i16 @s_uaddsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_uaddsat_i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_nc_u16 v0, s0, s1 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_nc_u16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result
}
@@ -1707,10 +1854,10 @@ define amdgpu_ps half @uaddsat_i16_sv(i16 inreg %lhs, i16 %rhs) {
; GFX9-NEXT: v_add_u16_e64 v0, s0, v0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: uaddsat_i16_sv:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_nc_u16 v0, s0, v0 clamp
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: uaddsat_i16_sv:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_nc_u16 v0, s0, v0 clamp
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)
%cast = bitcast i16 %result to half
ret half %cast
@@ -1737,10 +1884,10 @@ define amdgpu_ps half @uaddsat_i16_vs(i16 %lhs, i16 inreg %rhs) {
; GFX9-NEXT: v_add_u16_e64 v0, v0, s0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: uaddsat_i16_vs:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_nc_u16 v0, v0, s0 clamp
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: uaddsat_i16_vs:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_nc_u16 v0, v0, s0 clamp
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)
%cast = bitcast i16 %result to half
ret half %cast
@@ -1780,12 +1927,12 @@ define <2 x i16> @v_uaddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_uaddsat_v2i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_add_u16 v0, v0, v1 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_v2i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_pk_add_u16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
ret <2 x i16> %result
}
@@ -1830,11 +1977,11 @@ define amdgpu_ps i32 @s_uaddsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_uaddsat_v2i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_add_u16 v0, s0, s1 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_v2i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_pk_add_u16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to i32
ret i32 %cast
@@ -1873,10 +2020,10 @@ define amdgpu_ps float @uaddsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {
; GFX9-NEXT: v_pk_add_u16 v0, s0, v0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: uaddsat_v2i16_sv:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_add_u16 v0, s0, v0 clamp
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: uaddsat_v2i16_sv:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_pk_add_u16 v0, s0, v0 clamp
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to float
ret float %cast
@@ -1915,10 +2062,10 @@ define amdgpu_ps float @uaddsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
; GFX9-NEXT: v_pk_add_u16 v0, v0, s0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: uaddsat_v2i16_vs:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_add_u16 v0, v0, s0 clamp
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: uaddsat_v2i16_vs:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_pk_add_u16 v0, v0, s0 clamp
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to float
ret float %cast
@@ -1986,13 +2133,13 @@ define <2 x float> @v_uaddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX9-NEXT: v_pk_add_u16 v1, v1, v3 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_uaddsat_v4i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_add_u16 v0, v0, v2 clamp
-; GFX10-NEXT: v_pk_add_u16 v1, v1, v3 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_v4i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_pk_add_u16 v0, v0, v2 clamp
+; GFX10PLUS-NEXT: v_pk_add_u16 v1, v1, v3 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
%cast = bitcast <4 x i16> %result to <2 x float>
ret <2 x float> %cast
@@ -2064,13 +2211,13 @@ define amdgpu_ps <2 x i32> @s_uaddsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inre
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_uaddsat_v4i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_add_u16 v0, s0, s2 clamp
-; GFX10-NEXT: v_pk_add_u16 v1, s1, s3 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_v4i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_pk_add_u16 v0, s0, s2 clamp
+; GFX10PLUS-NEXT: v_pk_add_u16 v1, s1, s3 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
%cast = bitcast <4 x i16> %result to <2 x i32>
ret <2 x i32> %cast
@@ -2156,14 +2303,14 @@ define <3 x float> @v_uaddsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX9-NEXT: v_pk_add_u16 v2, v2, v5 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_uaddsat_v6i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_add_u16 v0, v0, v3 clamp
-; GFX10-NEXT: v_pk_add_u16 v1, v1, v4 clamp
-; GFX10-NEXT: v_pk_add_u16 v2, v2, v5 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_v6i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_pk_add_u16 v0, v0, v3 clamp
+; GFX10PLUS-NEXT: v_pk_add_u16 v1, v1, v4 clamp
+; GFX10PLUS-NEXT: v_pk_add_u16 v2, v2, v5 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <6 x i16> @llvm.uadd.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
%cast = bitcast <6 x i16> %result to <3 x float>
ret <3 x float> %cast
@@ -2261,15 +2408,15 @@ define amdgpu_ps <3 x i32> @s_uaddsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inre
; GFX9-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_uaddsat_v6i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_add_u16 v0, s0, s3 clamp
-; GFX10-NEXT: v_pk_add_u16 v1, s1, s4 clamp
-; GFX10-NEXT: v_pk_add_u16 v2, s2, s5 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_v6i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_pk_add_u16 v0, s0, s3 clamp
+; GFX10PLUS-NEXT: v_pk_add_u16 v1, s1, s4 clamp
+; GFX10PLUS-NEXT: v_pk_add_u16 v2, s2, s5 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <6 x i16> @llvm.uadd.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
%cast = bitcast <6 x i16> %result to <3 x i32>
ret <3 x i32> %cast
@@ -2361,15 +2508,15 @@ define <4 x float> @v_uaddsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
; GFX9-NEXT: v_pk_add_u16 v3, v3, v7 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_uaddsat_v8i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_add_u16 v0, v0, v4 clamp
-; GFX10-NEXT: v_pk_add_u16 v1, v1, v5 clamp
-; GFX10-NEXT: v_pk_add_u16 v2, v2, v6 clamp
-; GFX10-NEXT: v_pk_add_u16 v3, v3, v7 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_v8i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_pk_add_u16 v0, v0, v4 clamp
+; GFX10PLUS-NEXT: v_pk_add_u16 v1, v1, v5 clamp
+; GFX10PLUS-NEXT: v_pk_add_u16 v2, v2, v6 clamp
+; GFX10PLUS-NEXT: v_pk_add_u16 v3, v3, v7 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
%cast = bitcast <8 x i16> %result to <4 x float>
ret <4 x float> %cast
@@ -2493,17 +2640,17 @@ define amdgpu_ps <4 x i32> @s_uaddsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inre
; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_uaddsat_v8i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_add_u16 v0, s0, s4 clamp
-; GFX10-NEXT: v_pk_add_u16 v1, s1, s5 clamp
-; GFX10-NEXT: v_pk_add_u16 v2, s2, s6 clamp
-; GFX10-NEXT: v_pk_add_u16 v3, s3, s7 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_v8i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_pk_add_u16 v0, s0, s4 clamp
+; GFX10PLUS-NEXT: v_pk_add_u16 v1, s1, s5 clamp
+; GFX10PLUS-NEXT: v_pk_add_u16 v2, s2, s6 clamp
+; GFX10PLUS-NEXT: v_pk_add_u16 v3, s3, s7 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
%cast = bitcast <8 x i16> %result to <4 x i32>
ret <4 x i32> %cast
@@ -2565,16 +2712,16 @@ define i64 @v_uaddsat_i64(i64 %lhs, i64 %rhs) {
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_uaddsat_i64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
-; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc_lo
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_uaddsat_i64:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc_lo
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs)
ret i64 %result
}
@@ -2625,16 +2772,16 @@ define amdgpu_ps i64 @s_uaddsat_i64(i64 inreg %lhs, i64 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_uaddsat_i64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_add_u32 s0, s0, s2
-; GFX10-NEXT: s_addc_u32 s1, s1, s3
-; GFX10-NEXT: v_cmp_lt_u64_e64 s2, s[0:1], s[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, s0, -1, s2
-; GFX10-NEXT: v_cndmask_b32_e64 v1, s1, -1, s2
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_i64:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_add_u32 s0, s0, s2
+; GFX10PLUS-NEXT: s_addc_u32 s1, s1, s3
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s2, s[0:1], s[2:3]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, s0, -1, s2
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, s1, -1, s2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs)
ret i64 %result
}
@@ -2670,14 +2817,14 @@ define amdgpu_ps <2 x float> @uaddsat_i64_sv(i64 inreg %lhs, i64 %rhs) {
; GFX9-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: uaddsat_i64_sv:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, s0, v0
-; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[0:1]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, -1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc_lo
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: uaddsat_i64_sv:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_co_u32 v2, vcc_lo, s0, v0
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[0:1]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v2, -1, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc_lo
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs)
%cast = bitcast i64 %result to <2 x float>
ret <2 x float> %cast
@@ -2714,14 +2861,14 @@ define amdgpu_ps <2 x float> @uaddsat_i64_vs(i64 %lhs, i64 inreg %rhs) {
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: uaddsat_i64_vs:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, s0
-; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc_lo
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: uaddsat_i64_vs:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_co_u32 v0, vcc_lo, v0, s0
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc_lo
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs)
%cast = bitcast i64 %result to <2 x float>
ret <2 x float> %cast
@@ -2788,6 +2935,22 @@ define <2 x i64> @v_uaddsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, -1, s4
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, -1, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_uaddsat_v2i64:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
+; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v5, vcc_lo
+; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, v6
+; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v7, vcc_lo
+; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[6:7]
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, -1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, -1, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
ret <2 x i64> %result
}
@@ -2871,23 +3034,23 @@ define amdgpu_ps <2 x i64> @s_uaddsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inre
; GFX9-NEXT: v_readfirstlane_b32 s3, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_uaddsat_v2i64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_add_u32 s0, s0, s4
-; GFX10-NEXT: s_addc_u32 s1, s1, s5
-; GFX10-NEXT: s_add_u32 s2, s2, s6
-; GFX10-NEXT: s_addc_u32 s3, s3, s7
-; GFX10-NEXT: v_cmp_lt_u64_e64 s4, s[0:1], s[4:5]
-; GFX10-NEXT: v_cmp_lt_u64_e64 s5, s[2:3], s[6:7]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, s0, -1, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v1, s1, -1, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v2, s2, -1, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v3, s3, -1, s5
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_v2i64:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_add_u32 s0, s0, s4
+; GFX10PLUS-NEXT: s_addc_u32 s1, s1, s5
+; GFX10PLUS-NEXT: s_add_u32 s2, s2, s6
+; GFX10PLUS-NEXT: s_addc_u32 s3, s3, s7
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s4, s[0:1], s[4:5]
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s5, s[2:3], s[6:7]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, s0, -1, s4
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, s1, -1, s4
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, s2, -1, s5
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, s3, -1, s5
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
ret <2 x i64> %result
}
@@ -2995,32 +3158,32 @@ define amdgpu_ps i128 @s_uaddsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_uaddsat_i128:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_add_u32 s0, s0, s4
-; GFX10-NEXT: s_addc_u32 s1, s1, s5
-; GFX10-NEXT: s_addc_u32 s2, s2, s6
-; GFX10-NEXT: v_cmp_lt_u64_e64 s4, s[0:1], s[4:5]
-; GFX10-NEXT: s_addc_u32 s3, s3, s7
-; GFX10-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]
-; GFX10-NEXT: s_cselect_b32 s8, 1, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
-; GFX10-NEXT: v_cmp_lt_u64_e64 s4, s[2:3], s[6:7]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
-; GFX10-NEXT: s_and_b32 s4, 1, s8
-; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, s0, -1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, s1, -1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, s2, -1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v3, s3, -1, vcc_lo
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_i128:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_add_u32 s0, s0, s4
+; GFX10PLUS-NEXT: s_addc_u32 s1, s1, s5
+; GFX10PLUS-NEXT: s_addc_u32 s2, s2, s6
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s4, s[0:1], s[4:5]
+; GFX10PLUS-NEXT: s_addc_u32 s3, s3, s7
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]
+; GFX10PLUS-NEXT: s_cselect_b32 s8, 1, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s4, s[2:3], s[6:7]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
+; GFX10PLUS-NEXT: s_and_b32 s4, 1, s8
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10PLUS-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, s0, -1, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, s1, -1, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, s2, -1, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, s3, -1, vcc_lo
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i128 @llvm.uadd.sat.i128(i128 %lhs, i128 %rhs)
ret i128 %result
}
@@ -3095,25 +3258,25 @@ define amdgpu_ps <4 x float> @uaddsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX9-NEXT: v_cndmask_b32_e64 v3, v7, -1, vcc
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: uaddsat_i128_sv:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, s0, v0
-; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
-; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
-; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[0:1]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, -1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, -1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, -1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, -1, vcc_lo
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: uaddsat_i128_sv:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_co_u32 v4, vcc_lo, s0, v0
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[0:1]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[2:3]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10PLUS-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v4, -1, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v5, -1, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, v6, -1, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, v7, -1, vcc_lo
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i128 @llvm.uadd.sat.i128(i128 %lhs, i128 %rhs)
%cast = bitcast i128 %result to <4 x float>
ret <4 x float> %cast
@@ -3189,25 +3352,25 @@ define amdgpu_ps <4 x float> @uaddsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, -1, vcc
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: uaddsat_i128_vs:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, s0
-; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo
-; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
-; GFX10-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
-; GFX10-NEXT: v_and_b32_e32 v4, 1, v4
-; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, -1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, -1, vcc_lo
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: uaddsat_i128_vs:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_add_co_u32 v0, vcc_lo, v0, s0
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo
+; GFX10PLUS-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[2:3]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
+; GFX10PLUS-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, v2, -1, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, v3, -1, vcc_lo
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i128 @llvm.uadd.sat.i128(i128 %lhs, i128 %rhs)
%cast = bitcast i128 %result to <4 x float>
ret <4 x float> %cast
@@ -3362,6 +3525,44 @@ define <2 x i128> @v_uaddsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, -1, s4
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, -1, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_uaddsat_v2i128:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v8
+; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v9, vcc_lo
+; GFX11-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v10, vcc_lo
+; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v11, vcc_lo
+; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, v12
+; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v5, v13, vcc_lo
+; GFX11-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, v6, v14, vcc_lo
+; GFX11-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v7, v15, vcc_lo
+; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX11-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX11-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX11-NEXT: v_and_b32_e32 v8, 1, v8
+; GFX11-NEXT: v_cndmask_b32_e32 v9, v13, v12, vcc_lo
+; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-NEXT: v_and_b32_e32 v9, 1, v9
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc_lo
+; GFX11-NEXT: v_cmp_ne_u32_e64 s0, 0, v9
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, -1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, -1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, -1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, -1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, -1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, -1, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i128> @llvm.uadd.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
ret <2 x i128> %result
}
@@ -3559,55 +3760,55 @@ define amdgpu_ps <2 x i128> @s_uaddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX9-NEXT: v_readfirstlane_b32 s7, v3
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_uaddsat_v2i128:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_add_u32 s0, s0, s8
-; GFX10-NEXT: s_addc_u32 s1, s1, s9
-; GFX10-NEXT: s_addc_u32 s2, s2, s10
-; GFX10-NEXT: v_cmp_lt_u64_e64 s8, s[0:1], s[8:9]
-; GFX10-NEXT: s_addc_u32 s3, s3, s11
-; GFX10-NEXT: s_cmp_eq_u64 s[2:3], s[10:11]
-; GFX10-NEXT: s_cselect_b32 s16, 1, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s8
-; GFX10-NEXT: v_cmp_lt_u64_e64 s8, s[2:3], s[10:11]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s8
-; GFX10-NEXT: s_and_b32 s8, 1, s16
-; GFX10-NEXT: s_add_u32 s4, s4, s12
-; GFX10-NEXT: s_addc_u32 s5, s5, s13
-; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s8
-; GFX10-NEXT: v_cmp_lt_u64_e64 s9, s[4:5], s[12:13]
-; GFX10-NEXT: s_addc_u32 s6, s6, s14
-; GFX10-NEXT: s_addc_u32 s7, s7, s15
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT: s_cmp_eq_u64 s[6:7], s[14:15]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s9
-; GFX10-NEXT: v_cmp_lt_u64_e64 s9, s[6:7], s[14:15]
-; GFX10-NEXT: s_cselect_b32 s8, 1, 0
-; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT: s_and_b32 s8, 1, s8
-; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s8
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s9
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
-; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v0, s0, -1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, s2, -1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v3, s3, -1, vcc_lo
-; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v1, s1, -1, vcc_lo
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: v_cndmask_b32_e64 v4, s4, -1, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v5, s5, -1, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v6, s6, -1, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v7, s7, -1, s0
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s4, v4
-; GFX10-NEXT: v_readfirstlane_b32 s5, v5
-; GFX10-NEXT: v_readfirstlane_b32 s6, v6
-; GFX10-NEXT: v_readfirstlane_b32 s7, v7
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_uaddsat_v2i128:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_add_u32 s0, s0, s8
+; GFX10PLUS-NEXT: s_addc_u32 s1, s1, s9
+; GFX10PLUS-NEXT: s_addc_u32 s2, s2, s10
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s8, s[0:1], s[8:9]
+; GFX10PLUS-NEXT: s_addc_u32 s3, s3, s11
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[2:3], s[10:11]
+; GFX10PLUS-NEXT: s_cselect_b32 s16, 1, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, 0, 1, s8
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s8, s[2:3], s[10:11]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, 0, 1, s8
+; GFX10PLUS-NEXT: s_and_b32 s8, 1, s16
+; GFX10PLUS-NEXT: s_add_u32 s4, s4, s12
+; GFX10PLUS-NEXT: s_addc_u32 s5, s5, s13
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s8
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s9, s[4:5], s[12:13]
+; GFX10PLUS-NEXT: s_addc_u32 s6, s6, s14
+; GFX10PLUS-NEXT: s_addc_u32 s7, s7, s15
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[6:7], s[14:15]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, 0, 1, s9
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s9, s[6:7], s[14:15]
+; GFX10PLUS-NEXT: s_cselect_b32 s8, 1, 0
+; GFX10PLUS-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10PLUS-NEXT: s_and_b32 s8, 1, s8
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s8
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, 0, 1, s9
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX10PLUS-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, s0, -1, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, s2, -1, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, s3, -1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 s0, 0, v1
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, s1, -1, vcc_lo
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v4, s4, -1, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v5, s5, -1, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v6, s6, -1, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v7, s7, -1, s0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v4
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s5, v5
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s6, v6
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s7, v7
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <2 x i128> @llvm.uadd.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
ret <2 x i128> %result
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
index 3de02ca279fa7..da3ed3fb5d95a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
@@ -2,7 +2,8 @@
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -o - %s | FileCheck -check-prefix=GFX6 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s | FileCheck -check-prefix=GFX8 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
define i7 @v_usubsat_i7(i7 %lhs, i7 %rhs) {
; GFX6-LABEL: v_usubsat_i7:
@@ -33,15 +34,15 @@ define i7 @v_usubsat_i7(i7 %lhs, i7 %rhs) {
; GFX9-NEXT: v_lshrrev_b16_e32 v0, 9, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_usubsat_i7:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_lshlrev_b16 v0, 9, v0
-; GFX10-NEXT: v_lshlrev_b16 v1, 9, v1
-; GFX10-NEXT: v_sub_nc_u16 v0, v0, v1 clamp
-; GFX10-NEXT: v_lshrrev_b16 v0, 9, v0
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_i7:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_lshlrev_b16 v0, 9, v0
+; GFX10PLUS-NEXT: v_lshlrev_b16 v1, 9, v1
+; GFX10PLUS-NEXT: v_sub_nc_u16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT: v_lshrrev_b16 v0, 9, v0
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call i7 @llvm.usub.sat.i7(i7 %lhs, i7 %rhs)
ret i7 %result
}
@@ -78,15 +79,15 @@ define amdgpu_ps i7 @s_usubsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_usubsat_i7:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_bfe_u32 s2, 9, 0x100000
-; GFX10-NEXT: s_lshl_b32 s0, s0, s2
-; GFX10-NEXT: s_lshl_b32 s1, s1, s2
-; GFX10-NEXT: v_sub_nc_u16 v0, s0, s1 clamp
-; GFX10-NEXT: v_lshrrev_b16 v0, 9, v0
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_i7:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_bfe_u32 s2, 9, 0x100000
+; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, s2
+; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, s2
+; GFX10PLUS-NEXT: v_sub_nc_u16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT: v_lshrrev_b16 v0, 9, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i7 @llvm.usub.sat.i7(i7 %lhs, i7 %rhs)
ret i7 %result
}
@@ -120,15 +121,15 @@ define i8 @v_usubsat_i8(i8 %lhs, i8 %rhs) {
; GFX9-NEXT: v_lshrrev_b16_e32 v0, 8, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_usubsat_i8:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_lshlrev_b16 v0, 8, v0
-; GFX10-NEXT: v_lshlrev_b16 v1, 8, v1
-; GFX10-NEXT: v_sub_nc_u16 v0, v0, v1 clamp
-; GFX10-NEXT: v_lshrrev_b16 v0, 8, v0
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_i8:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_lshlrev_b16 v0, 8, v0
+; GFX10PLUS-NEXT: v_lshlrev_b16 v1, 8, v1
+; GFX10PLUS-NEXT: v_sub_nc_u16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT: v_lshrrev_b16 v0, 8, v0
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call i8 @llvm.usub.sat.i8(i8 %lhs, i8 %rhs)
ret i8 %result
}
@@ -165,15 +166,15 @@ define amdgpu_ps i8 @s_usubsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_usubsat_i8:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_bfe_u32 s2, 8, 0x100000
-; GFX10-NEXT: s_lshl_b32 s0, s0, s2
-; GFX10-NEXT: s_lshl_b32 s1, s1, s2
-; GFX10-NEXT: v_sub_nc_u16 v0, s0, s1 clamp
-; GFX10-NEXT: v_lshrrev_b16 v0, 8, v0
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_i8:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_bfe_u32 s2, 8, 0x100000
+; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, s2
+; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, s2
+; GFX10PLUS-NEXT: v_sub_nc_u16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT: v_lshrrev_b16 v0, 8, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i8 @llvm.usub.sat.i8(i8 %lhs, i8 %rhs)
ret i8 %result
}
@@ -248,6 +249,27 @@ define i16 @v_usubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX10-NEXT: v_and_b32_sdwa v1, v0, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_usubsat_v2i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_lshrrev_b32_e32 v2, 8, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT: v_and_or_b32 v0, 0xffff, v0, v2
+; GFX11-NEXT: v_and_or_b32 v1, 0xffff, v1, v3
+; GFX11-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_sub_u16 v0, v0, v1 clamp
+; GFX11-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8>
%result = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
@@ -337,6 +359,30 @@ define amdgpu_ps i16 @s_usubsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_usubsat_v2i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshr_b32 s2, s0, 8
+; GFX11-NEXT: s_lshr_b32 s3, s1, 8
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s2
+; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s3
+; GFX11-NEXT: s_lshr_b32 s2, s0, 16
+; GFX11-NEXT: s_lshr_b32 s3, s1, 16
+; GFX11-NEXT: s_lshl_b32 s0, s0, 0x80008
+; GFX11-NEXT: s_lshl_b32 s2, s2, 8
+; GFX11-NEXT: s_lshl_b32 s1, s1, 0x80008
+; GFX11-NEXT: s_lshl_b32 s3, s3, 8
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s2
+; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s3
+; GFX11-NEXT: v_pk_sub_u16 v0, s0, s1 clamp
+; GFX11-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: ; return to shader part epilog
%lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8>
%result = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
@@ -481,6 +527,42 @@ define i32 @v_usubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX10-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_usubsat_v4i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_lshrrev_b32_e32 v2, 8, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v5, 24, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v6, 24, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-NEXT: v_and_or_b32 v0, 0xffff, v0, v2
+; GFX11-NEXT: v_and_or_b32 v1, 0xffff, v1, v3
+; GFX11-NEXT: v_and_or_b32 v2, 0xffff, v4, v5
+; GFX11-NEXT: v_and_or_b32 v3, 0xffff, v7, v6
+; GFX11-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_sub_u16 v0, v0, v1 clamp
+; GFX11-NEXT: v_pk_sub_u16 v1, v2, v3 clamp
+; GFX11-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT: v_bfe_u32 v2, v0, 16, 8
+; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v1
+; GFX11-NEXT: v_bfe_u32 v1, v1, 16, 8
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; GFX11-NEXT: v_and_or_b32 v0, v0, 0xff, v2
+; GFX11-NEXT: v_or3_b32 v0, v0, v3, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8>
%result = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
@@ -650,6 +732,47 @@ define amdgpu_ps i32 @s_usubsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) {
; GFX10-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_usubsat_v4i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshr_b32 s2, s0, 8
+; GFX11-NEXT: s_lshr_b32 s4, s1, 8
+; GFX11-NEXT: s_pack_ll_b32_b16 s2, s0, s2
+; GFX11-NEXT: s_pack_ll_b32_b16 s4, s1, s4
+; GFX11-NEXT: s_lshr_b32 s6, s2, 16
+; GFX11-NEXT: s_lshl_b32 s2, s2, 0x80008
+; GFX11-NEXT: s_lshl_b32 s6, s6, 8
+; GFX11-NEXT: s_lshr_b32 s3, s0, 24
+; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s6
+; GFX11-NEXT: s_lshr_b32 s6, s4, 16
+; GFX11-NEXT: s_lshr_b32 s5, s1, 24
+; GFX11-NEXT: s_lshl_b32 s4, s4, 0x80008
+; GFX11-NEXT: s_lshl_b32 s6, s6, 8
+; GFX11-NEXT: s_pack_hl_b32_b16 s0, s0, s3
+; GFX11-NEXT: s_pack_hl_b32_b16 s1, s1, s5
+; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s6
+; GFX11-NEXT: s_lshr_b32 s3, s0, 16
+; GFX11-NEXT: s_lshr_b32 s5, s1, 16
+; GFX11-NEXT: v_pk_sub_u16 v0, s2, s4 clamp
+; GFX11-NEXT: s_lshl_b32 s0, s0, 0x80008
+; GFX11-NEXT: s_lshl_b32 s3, s3, 8
+; GFX11-NEXT: s_lshl_b32 s1, s1, 0x80008
+; GFX11-NEXT: s_lshl_b32 s2, s5, 8
+; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s3
+; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s2
+; GFX11-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_sub_u16 v1, s0, s1 clamp
+; GFX11-NEXT: v_bfe_u32 v2, v0, 16, 8
+; GFX11-NEXT: v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v1
+; GFX11-NEXT: v_bfe_u32 v1, v1, 16, 8
+; GFX11-NEXT: v_and_or_b32 v0, v0, 0xff, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; GFX11-NEXT: v_or3_b32 v0, v0, v2, v1
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: ; return to shader part epilog
%lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8>
%result = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
@@ -686,15 +809,15 @@ define i24 @v_usubsat_i24(i24 %lhs, i24 %rhs) {
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 8, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_usubsat_i24:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, v1 clamp
-; GFX10-NEXT: v_lshrrev_b32_e32 v0, 8, v0
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_i24:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, v0, v1 clamp
+; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, 8, v0
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call i24 @llvm.usub.sat.i24(i24 %lhs, i24 %rhs)
ret i24 %result
}
@@ -729,14 +852,14 @@ define amdgpu_ps i24 @s_usubsat_i24(i24 inreg %lhs, i24 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_usubsat_i24:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_lshl_b32 s0, s0, 8
-; GFX10-NEXT: s_lshl_b32 s1, s1, 8
-; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, s1 clamp
-; GFX10-NEXT: v_lshrrev_b32_e32 v0, 8, v0
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_i24:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, 8
+; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, 8
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, s0, s1 clamp
+; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, 8, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i24 @llvm.usub.sat.i24(i24 %lhs, i24 %rhs)
ret i24 %result
}
@@ -761,12 +884,12 @@ define i32 @v_usubsat_i32(i32 %lhs, i32 %rhs) {
; GFX9-NEXT: v_sub_u32_e64 v0, v0, v1 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_usubsat_i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, v1 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, v0, v1 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)
ret i32 %result
}
@@ -792,11 +915,11 @@ define amdgpu_ps i32 @s_usubsat_i32(i32 inreg %lhs, i32 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_usubsat_i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, s1 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, s0, s1 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)
ret i32 %result
}
@@ -818,10 +941,10 @@ define amdgpu_ps float @usubsat_i32_sv(i32 inreg %lhs, i32 %rhs) {
; GFX9-NEXT: v_sub_u32_e64 v0, s0, v0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: usubsat_i32_sv:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, v0 clamp
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: usubsat_i32_sv:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, s0, v0 clamp
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)
%cast = bitcast i32 %result to float
ret float %cast
@@ -844,10 +967,10 @@ define amdgpu_ps float @usubsat_i32_vs(i32 %lhs, i32 inreg %rhs) {
; GFX9-NEXT: v_sub_u32_e64 v0, v0, s0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: usubsat_i32_vs:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, s0 clamp
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: usubsat_i32_vs:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, v0, s0 clamp
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)
%cast = bitcast i32 %result to float
ret float %cast
@@ -877,13 +1000,13 @@ define <2 x i32> @v_usubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
; GFX9-NEXT: v_sub_u32_e64 v1, v1, v3 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_usubsat_v2i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, v2 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v1, v1, v3 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_v2i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, v0, v2 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v1, v1, v3 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
ret <2 x i32> %result
}
@@ -917,13 +1040,13 @@ define amdgpu_ps <2 x i32> @s_usubsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inre
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_usubsat_v2i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, s2 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v1, s1, s3 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_v2i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, s0, s2 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v1, s1, s3 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
ret <2 x i32> %result
}
@@ -956,14 +1079,14 @@ define <3 x i32> @v_usubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
; GFX9-NEXT: v_sub_u32_e64 v2, v2, v5 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_usubsat_v3i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, v3 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v1, v1, v4 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v2, v2, v5 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_v3i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, v0, v3 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v1, v1, v4 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v2, v2, v5 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x i32> @llvm.usub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
ret <3 x i32> %result
}
@@ -1005,15 +1128,15 @@ define amdgpu_ps <3 x i32> @s_usubsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inre
; GFX9-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_usubsat_v3i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, s3 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v1, s1, s4 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v2, s2, s5 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_v3i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, s0, s3 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v1, s1, s4 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v2, s2, s5 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <3 x i32> @llvm.usub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
ret <3 x i32> %result
}
@@ -1050,15 +1173,15 @@ define <4 x i32> @v_usubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; GFX9-NEXT: v_sub_u32_e64 v3, v3, v7 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_usubsat_v4i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, v4 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v1, v1, v5 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v2, v2, v6 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v3, v3, v7 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_v4i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, v0, v4 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v1, v1, v5 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v2, v2, v6 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v3, v3, v7 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
ret <4 x i32> %result
}
@@ -1108,17 +1231,17 @@ define amdgpu_ps <4 x i32> @s_usubsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inre
; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_usubsat_v4i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, s4 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v1, s1, s5 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v2, s2, s6 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v3, s3, s7 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_v4i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, s0, s4 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v1, s1, s5 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v2, s2, s6 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v3, s3, s7 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
ret <4 x i32> %result
}
@@ -1159,16 +1282,16 @@ define <5 x i32> @v_usubsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
; GFX9-NEXT: v_sub_u32_e64 v4, v4, v9 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_usubsat_v5i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, v5 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v1, v1, v6 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v2, v2, v7 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v3, v3, v8 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v4, v4, v9 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_v5i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, v0, v5 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v1, v1, v6 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v2, v2, v7 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v3, v3, v8 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v4, v4, v9 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <5 x i32> @llvm.usub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
ret <5 x i32> %result
}
@@ -1226,19 +1349,19 @@ define amdgpu_ps <5 x i32> @s_usubsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inre
; GFX9-NEXT: v_readfirstlane_b32 s4, v4
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_usubsat_v5i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, s5 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v1, s1, s6 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v2, s2, s7 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v3, s3, s8 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v4, s4, s9 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: v_readfirstlane_b32 s4, v4
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_v5i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, s0, s5 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v1, s1, s6 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v2, s2, s7 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v3, s3, s8 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v4, s4, s9 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v4
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <5 x i32> @llvm.usub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
ret <5 x i32> %result
}
@@ -1352,6 +1475,30 @@ define <16 x i32> @v_usubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_sub_nc_u32_e64 v15, v15, v31 clamp
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_usubsat_v16i32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_b32 v31, off, s32
+; GFX11-NEXT: v_sub_nc_u32_e64 v0, v0, v16 clamp
+; GFX11-NEXT: v_sub_nc_u32_e64 v1, v1, v17 clamp
+; GFX11-NEXT: v_sub_nc_u32_e64 v2, v2, v18 clamp
+; GFX11-NEXT: v_sub_nc_u32_e64 v3, v3, v19 clamp
+; GFX11-NEXT: v_sub_nc_u32_e64 v4, v4, v20 clamp
+; GFX11-NEXT: v_sub_nc_u32_e64 v5, v5, v21 clamp
+; GFX11-NEXT: v_sub_nc_u32_e64 v6, v6, v22 clamp
+; GFX11-NEXT: v_sub_nc_u32_e64 v7, v7, v23 clamp
+; GFX11-NEXT: v_sub_nc_u32_e64 v8, v8, v24 clamp
+; GFX11-NEXT: v_sub_nc_u32_e64 v9, v9, v25 clamp
+; GFX11-NEXT: v_sub_nc_u32_e64 v10, v10, v26 clamp
+; GFX11-NEXT: v_sub_nc_u32_e64 v11, v11, v27 clamp
+; GFX11-NEXT: v_sub_nc_u32_e64 v12, v12, v28 clamp
+; GFX11-NEXT: v_sub_nc_u32_e64 v13, v13, v29 clamp
+; GFX11-NEXT: v_sub_nc_u32_e64 v14, v14, v30 clamp
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_sub_nc_u32_e64 v15, v15, v31 clamp
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result
}
@@ -1497,41 +1644,41 @@ define amdgpu_ps <16 x i32> @s_usubsat_v16i32(<16 x i32> inreg %lhs, <16 x i32>
; GFX9-NEXT: v_readfirstlane_b32 s15, v15
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_usubsat_v16i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, s16 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v1, s1, s17 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v2, s2, s18 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v3, s3, s19 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v4, s4, s20 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v5, s5, s21 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v6, s6, s22 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v7, s7, s23 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v8, s8, s24 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v9, s9, s25 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v10, s10, s26 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v11, s11, s27 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v12, s12, s28 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v13, s13, s29 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v14, s14, s30 clamp
-; GFX10-NEXT: v_sub_nc_u32_e64 v15, s15, s31 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: v_readfirstlane_b32 s4, v4
-; GFX10-NEXT: v_readfirstlane_b32 s5, v5
-; GFX10-NEXT: v_readfirstlane_b32 s6, v6
-; GFX10-NEXT: v_readfirstlane_b32 s7, v7
-; GFX10-NEXT: v_readfirstlane_b32 s8, v8
-; GFX10-NEXT: v_readfirstlane_b32 s9, v9
-; GFX10-NEXT: v_readfirstlane_b32 s10, v10
-; GFX10-NEXT: v_readfirstlane_b32 s11, v11
-; GFX10-NEXT: v_readfirstlane_b32 s12, v12
-; GFX10-NEXT: v_readfirstlane_b32 s13, v13
-; GFX10-NEXT: v_readfirstlane_b32 s14, v14
-; GFX10-NEXT: v_readfirstlane_b32 s15, v15
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_v16i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, s0, s16 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v1, s1, s17 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v2, s2, s18 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v3, s3, s19 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v4, s4, s20 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v5, s5, s21 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v6, s6, s22 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v7, s7, s23 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v8, s8, s24 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v9, s9, s25 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v10, s10, s26 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v11, s11, s27 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v12, s12, s28 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v13, s13, s29 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v14, s14, s30 clamp
+; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v15, s15, s31 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v4
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s5, v5
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s6, v6
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s7, v7
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s8, v8
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s9, v9
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s10, v10
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s11, v11
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s12, v12
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s13, v13
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s14, v14
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s15, v15
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result
}
@@ -1559,12 +1706,12 @@ define i16 @v_usubsat_i16(i16 %lhs, i16 %rhs) {
; GFX9-NEXT: v_sub_u16_e64 v0, v0, v1 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_usubsat_i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_sub_nc_u16 v0, v0, v1 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_sub_nc_u16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result
}
@@ -1593,11 +1740,11 @@ define amdgpu_ps i16 @s_usubsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_usubsat_i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_nc_u16 v0, s0, s1 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_nc_u16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result
}
@@ -1622,10 +1769,10 @@ define amdgpu_ps half @usubsat_i16_sv(i16 inreg %lhs, i16 %rhs) {
; GFX9-NEXT: v_sub_u16_e64 v0, s0, v0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: usubsat_i16_sv:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_nc_u16 v0, s0, v0 clamp
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: usubsat_i16_sv:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_nc_u16 v0, s0, v0 clamp
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
%cast = bitcast i16 %result to half
ret half %cast
@@ -1651,10 +1798,10 @@ define amdgpu_ps half @usubsat_i16_vs(i16 %lhs, i16 inreg %rhs) {
; GFX9-NEXT: v_sub_u16_e64 v0, v0, s0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: usubsat_i16_vs:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_nc_u16 v0, v0, s0 clamp
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: usubsat_i16_vs:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_nc_u16 v0, v0, s0 clamp
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
%cast = bitcast i16 %result to half
ret half %cast
@@ -1692,12 +1839,12 @@ define <2 x i16> @v_usubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX9-NEXT: v_pk_sub_u16 v0, v0, v1 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_usubsat_v2i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_sub_u16 v0, v0, v1 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_v2i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_pk_sub_u16 v0, v0, v1 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
ret <2 x i16> %result
}
@@ -1740,11 +1887,11 @@ define amdgpu_ps i32 @s_usubsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_usubsat_v2i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_sub_u16 v0, s0, s1 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_v2i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_pk_sub_u16 v0, s0, s1 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to i32
ret i32 %cast
@@ -1781,10 +1928,10 @@ define amdgpu_ps float @usubsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {
; GFX9-NEXT: v_pk_sub_u16 v0, s0, v0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: usubsat_v2i16_sv:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_sub_u16 v0, s0, v0 clamp
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: usubsat_v2i16_sv:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_pk_sub_u16 v0, s0, v0 clamp
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to float
ret float %cast
@@ -1821,10 +1968,10 @@ define amdgpu_ps float @usubsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
; GFX9-NEXT: v_pk_sub_u16 v0, v0, s0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: usubsat_v2i16_vs:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_sub_u16 v0, v0, s0 clamp
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: usubsat_v2i16_vs:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_pk_sub_u16 v0, v0, s0 clamp
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to float
ret float %cast
@@ -1888,13 +2035,13 @@ define <2 x float> @v_usubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX9-NEXT: v_pk_sub_u16 v1, v1, v3 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_usubsat_v4i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_sub_u16 v0, v0, v2 clamp
-; GFX10-NEXT: v_pk_sub_u16 v1, v1, v3 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_v4i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_pk_sub_u16 v0, v0, v2 clamp
+; GFX10PLUS-NEXT: v_pk_sub_u16 v1, v1, v3 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
%cast = bitcast <4 x i16> %result to <2 x float>
ret <2 x float> %cast
@@ -1962,13 +2109,13 @@ define amdgpu_ps <2 x i32> @s_usubsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inre
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_usubsat_v4i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_sub_u16 v0, s0, s2 clamp
-; GFX10-NEXT: v_pk_sub_u16 v1, s1, s3 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_v4i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_pk_sub_u16 v0, s0, s2 clamp
+; GFX10PLUS-NEXT: v_pk_sub_u16 v1, s1, s3 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
%cast = bitcast <4 x i16> %result to <2 x i32>
ret <2 x i32> %cast
@@ -2048,14 +2195,14 @@ define <3 x float> @v_usubsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX9-NEXT: v_pk_sub_u16 v2, v2, v5 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_usubsat_v6i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_sub_u16 v0, v0, v3 clamp
-; GFX10-NEXT: v_pk_sub_u16 v1, v1, v4 clamp
-; GFX10-NEXT: v_pk_sub_u16 v2, v2, v5 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_v6i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_pk_sub_u16 v0, v0, v3 clamp
+; GFX10PLUS-NEXT: v_pk_sub_u16 v1, v1, v4 clamp
+; GFX10PLUS-NEXT: v_pk_sub_u16 v2, v2, v5 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <6 x i16> @llvm.usub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
%cast = bitcast <6 x i16> %result to <3 x float>
ret <3 x float> %cast
@@ -2147,15 +2294,15 @@ define amdgpu_ps <3 x i32> @s_usubsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inre
; GFX9-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_usubsat_v6i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_sub_u16 v0, s0, s3 clamp
-; GFX10-NEXT: v_pk_sub_u16 v1, s1, s4 clamp
-; GFX10-NEXT: v_pk_sub_u16 v2, s2, s5 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_v6i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_pk_sub_u16 v0, s0, s3 clamp
+; GFX10PLUS-NEXT: v_pk_sub_u16 v1, s1, s4 clamp
+; GFX10PLUS-NEXT: v_pk_sub_u16 v2, s2, s5 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <6 x i16> @llvm.usub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
%cast = bitcast <6 x i16> %result to <3 x i32>
ret <3 x i32> %cast
@@ -2239,15 +2386,15 @@ define <4 x float> @v_usubsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
; GFX9-NEXT: v_pk_sub_u16 v3, v3, v7 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_usubsat_v8i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_sub_u16 v0, v0, v4 clamp
-; GFX10-NEXT: v_pk_sub_u16 v1, v1, v5 clamp
-; GFX10-NEXT: v_pk_sub_u16 v2, v2, v6 clamp
-; GFX10-NEXT: v_pk_sub_u16 v3, v3, v7 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_v8i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_pk_sub_u16 v0, v0, v4 clamp
+; GFX10PLUS-NEXT: v_pk_sub_u16 v1, v1, v5 clamp
+; GFX10PLUS-NEXT: v_pk_sub_u16 v2, v2, v6 clamp
+; GFX10PLUS-NEXT: v_pk_sub_u16 v3, v3, v7 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
%cast = bitcast <8 x i16> %result to <4 x float>
ret <4 x float> %cast
@@ -2363,17 +2510,17 @@ define amdgpu_ps <4 x i32> @s_usubsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inre
; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_usubsat_v8i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_sub_u16 v0, s0, s4 clamp
-; GFX10-NEXT: v_pk_sub_u16 v1, s1, s5 clamp
-; GFX10-NEXT: v_pk_sub_u16 v2, s2, s6 clamp
-; GFX10-NEXT: v_pk_sub_u16 v3, s3, s7 clamp
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_v8i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_pk_sub_u16 v0, s0, s4 clamp
+; GFX10PLUS-NEXT: v_pk_sub_u16 v1, s1, s5 clamp
+; GFX10PLUS-NEXT: v_pk_sub_u16 v2, s2, s6 clamp
+; GFX10PLUS-NEXT: v_pk_sub_u16 v3, s3, s7 clamp
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
%cast = bitcast <8 x i16> %result to <4 x i32>
ret <4 x i32> %cast
@@ -2435,16 +2582,16 @@ define i64 @v_usubsat_i64(i64 %lhs, i64 %rhs) {
; GFX9-NEXT: v_cndmask_b32_e64 v1, v5, 0, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_usubsat_i64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v2
-; GFX10-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo
-; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0, vcc_lo
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_usubsat_i64:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v2
+; GFX10PLUS-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v5, 0, vcc_lo
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)
ret i64 %result
}
@@ -2495,16 +2642,16 @@ define amdgpu_ps i64 @s_usubsat_i64(i64 inreg %lhs, i64 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_usubsat_i64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_sub_u32 s4, s0, s2
-; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[0:1], s[2:3]
-; GFX10-NEXT: s_subb_u32 s1, s1, s3
-; GFX10-NEXT: v_cndmask_b32_e64 v0, s4, 0, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, s1, 0, s0
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_i64:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_sub_u32 s4, s0, s2
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s0, s[0:1], s[2:3]
+; GFX10PLUS-NEXT: s_subb_u32 s1, s1, s3
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, s4, 0, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, s1, 0, s0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)
ret i64 %result
}
@@ -2540,14 +2687,14 @@ define amdgpu_ps <2 x float> @usubsat_i64_sv(i64 inreg %lhs, i64 %rhs) {
; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: usubsat_i64_sv:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, s0, v0
-; GFX10-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, s[0:1], v[0:1]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: usubsat_i64_sv:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_co_u32 v2, vcc_lo, s0, v0
+; GFX10PLUS-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e32 vcc_lo, s[0:1], v[0:1]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)
%cast = bitcast i64 %result to <2 x float>
ret <2 x float> %cast
@@ -2584,14 +2731,14 @@ define amdgpu_ps <2 x float> @usubsat_i64_vs(i64 %lhs, i64 inreg %rhs) {
; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: usubsat_i64_vs:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v0, s0
-; GFX10-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: usubsat_i64_vs:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_sub_co_u32 v2, vcc_lo, v0, s0
+; GFX10PLUS-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)
%cast = bitcast i64 %result to <2 x float>
ret <2 x float> %cast
@@ -2658,6 +2805,22 @@ define <2 x i64> @v_usubsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, 0, s4
; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, 0, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_usubsat_v2i64:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_sub_co_u32 v8, vcc_lo, v0, v4
+; GFX11-NEXT: v_sub_co_ci_u32_e32 v9, vcc_lo, v1, v5, vcc_lo
+; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT: v_sub_co_u32 v4, s0, v2, v6
+; GFX11-NEXT: v_sub_co_ci_u32_e64 v5, s0, v3, v7, s0
+; GFX11-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[6:7]
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v9, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, 0, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v5, 0, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
ret <2 x i64> %result
}
@@ -2741,23 +2904,23 @@ define amdgpu_ps <2 x i64> @s_usubsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inre
; GFX9-NEXT: v_readfirstlane_b32 s3, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_usubsat_v2i64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_sub_u32 s8, s0, s4
-; GFX10-NEXT: v_cmp_lt_u64_e64 s4, s[0:1], s[4:5]
-; GFX10-NEXT: s_subb_u32 s1, s1, s5
-; GFX10-NEXT: s_sub_u32 s0, s2, s6
-; GFX10-NEXT: v_cmp_lt_u64_e64 s2, s[2:3], s[6:7]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, s1, 0, s4
-; GFX10-NEXT: s_subb_u32 s1, s3, s7
-; GFX10-NEXT: v_cndmask_b32_e64 v0, s8, 0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v2, s0, 0, s2
-; GFX10-NEXT: v_cndmask_b32_e64 v3, s1, 0, s2
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_v2i64:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_sub_u32 s8, s0, s4
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s4, s[0:1], s[4:5]
+; GFX10PLUS-NEXT: s_subb_u32 s1, s1, s5
+; GFX10PLUS-NEXT: s_sub_u32 s0, s2, s6
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s2, s[2:3], s[6:7]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, s1, 0, s4
+; GFX10PLUS-NEXT: s_subb_u32 s1, s3, s7
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, s8, 0, s4
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, s0, 0, s2
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, s1, 0, s2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
ret <2 x i64> %result
}
@@ -2865,32 +3028,32 @@ define amdgpu_ps i128 @s_usubsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_usubsat_i128:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_sub_u32 s8, s0, s4
-; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[0:1], s[4:5]
-; GFX10-NEXT: s_subb_u32 s9, s1, s5
-; GFX10-NEXT: s_subb_u32 s10, s2, s6
-; GFX10-NEXT: s_subb_u32 s11, s3, s7
-; GFX10-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[2:3], s[6:7]
-; GFX10-NEXT: s_cselect_b32 s12, 1, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
-; GFX10-NEXT: s_and_b32 s0, 1, s12
-; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, s8, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, s9, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, s10, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v3, s11, 0, vcc_lo
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_i128:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_sub_u32 s8, s0, s4
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s0, s[0:1], s[4:5]
+; GFX10PLUS-NEXT: s_subb_u32 s9, s1, s5
+; GFX10PLUS-NEXT: s_subb_u32 s10, s2, s6
+; GFX10PLUS-NEXT: s_subb_u32 s11, s3, s7
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s0, s[2:3], s[6:7]
+; GFX10PLUS-NEXT: s_cselect_b32 s12, 1, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX10PLUS-NEXT: s_and_b32 s0, 1, s12
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10PLUS-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, s8, 0, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, s9, 0, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, s10, 0, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, s11, 0, vcc_lo
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i128 @llvm.usub.sat.i128(i128 %lhs, i128 %rhs)
ret i128 %result
}
@@ -2965,25 +3128,25 @@ define amdgpu_ps <4 x float> @usubsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX9-NEXT: v_cndmask_b32_e64 v3, v7, 0, vcc
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: usubsat_i128_sv:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, s[0:1], v[0:1]
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, s[2:3], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
-; GFX10-NEXT: v_sub_co_u32 v0, vcc_lo, s0, v0
-; GFX10-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT: v_and_b32_e32 v4, 1, v4
-; GFX10-NEXT: v_sub_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo
-; GFX10-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
-; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v4
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, 0, s0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: usubsat_i128_sv:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e32 vcc_lo, s[0:1], v[0:1]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e32 vcc_lo, s[2:3], v[2:3]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
+; GFX10PLUS-NEXT: v_sub_co_u32 v0, vcc_lo, s0, v0
+; GFX10PLUS-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX10PLUS-NEXT: v_sub_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo
+; GFX10PLUS-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 s0, 0, v4
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, 0, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, 0, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, v3, 0, s0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i128 @llvm.usub.sat.i128(i128 %lhs, i128 %rhs)
%cast = bitcast i128 %result to <4 x float>
ret <4 x float> %cast
@@ -3059,25 +3222,25 @@ define amdgpu_ps <4 x float> @usubsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
; GFX9-NEXT: v_cndmask_b32_e64 v3, v7, 0, vcc
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: usubsat_i128_vs:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
-; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
-; GFX10-NEXT: v_sub_co_u32 v0, vcc_lo, v0, s0
-; GFX10-NEXT: v_subrev_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT: v_and_b32_e32 v4, 1, v4
-; GFX10-NEXT: v_subrev_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo
-; GFX10-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
-; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v4
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, 0, s0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: usubsat_i128_vs:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[2:3]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
+; GFX10PLUS-NEXT: v_sub_co_u32 v0, vcc_lo, v0, s0
+; GFX10PLUS-NEXT: v_subrev_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
+; GFX10PLUS-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX10PLUS-NEXT: v_subrev_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo
+; GFX10PLUS-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 s0, 0, v4
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, 0, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, 0, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, v3, 0, s0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i128 @llvm.usub.sat.i128(i128 %lhs, i128 %rhs)
%cast = bitcast i128 %result to <4 x float>
ret <4 x float> %cast
@@ -3232,6 +3395,44 @@ define <2 x i128> @v_usubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, 0, s5
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, 0, s5
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_usubsat_v2i128:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX11-NEXT: v_cmp_eq_u64_e64 s1, v[6:7], v[14:15]
+; GFX11-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
+; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[10:11]
+; GFX11-NEXT: v_cndmask_b32_e32 v16, v17, v16, vcc_lo
+; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX11-NEXT: v_and_b32_e32 v16, 1, v16
+; GFX11-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
+; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX11-NEXT: v_cmp_ne_u32_e64 s0, 0, v16
+; GFX11-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo
+; GFX11-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v8
+; GFX11-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v9, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v18, v17, s1
+; GFX11-NEXT: v_sub_co_ci_u32_e32 v2, vcc_lo, v2, v10, vcc_lo
+; GFX11-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, v3, v11, vcc_lo
+; GFX11-NEXT: v_sub_co_u32 v4, vcc_lo, v4, v12
+; GFX11-NEXT: v_and_b32_e32 v8, 1, v8
+; GFX11-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, v5, v13, vcc_lo
+; GFX11-NEXT: v_sub_co_ci_u32_e32 v6, vcc_lo, v6, v14, vcc_lo
+; GFX11-NEXT: v_cmp_ne_u32_e64 s1, 0, v8
+; GFX11-NEXT: v_sub_co_ci_u32_e32 v7, vcc_lo, v7, v15, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, 0, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, 0, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, 0, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, 0, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, 0, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, 0, s1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i128> @llvm.usub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
ret <2 x i128> %result
}
@@ -3429,55 +3630,55 @@ define amdgpu_ps <2 x i128> @s_usubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX9-NEXT: v_readfirstlane_b32 s7, v3
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_usubsat_v2i128:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_sub_u32 s16, s0, s8
-; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[0:1], s[8:9]
-; GFX10-NEXT: s_subb_u32 s17, s1, s9
-; GFX10-NEXT: s_subb_u32 s18, s2, s10
-; GFX10-NEXT: s_subb_u32 s19, s3, s11
-; GFX10-NEXT: s_cmp_eq_u64 s[2:3], s[10:11]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[2:3], s[10:11]
-; GFX10-NEXT: s_cselect_b32 s20, 1, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
-; GFX10-NEXT: s_and_b32 s0, 1, s20
-; GFX10-NEXT: s_sub_u32 s2, s4, s12
-; GFX10-NEXT: v_cmp_lt_u64_e64 s4, s[4:5], s[12:13]
-; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT: s_subb_u32 s1, s5, s13
-; GFX10-NEXT: s_subb_u32 s8, s6, s14
-; GFX10-NEXT: s_subb_u32 s3, s7, s15
-; GFX10-NEXT: s_cmp_eq_u64 s[6:7], s[14:15]
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
-; GFX10-NEXT: v_cmp_lt_u64_e64 s4, s[6:7], s[14:15]
-; GFX10-NEXT: s_cselect_b32 s0, 1, 0
-; GFX10-NEXT: s_and_b32 s0, 1, s0
-; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
-; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v0, s16, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, s18, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v3, s19, 0, vcc_lo
-; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v1, s17, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v4, s2, 0, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v5, s1, 0, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v6, s8, 0, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v7, s3, 0, s0
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: v_readfirstlane_b32 s4, v4
-; GFX10-NEXT: v_readfirstlane_b32 s5, v5
-; GFX10-NEXT: v_readfirstlane_b32 s6, v6
-; GFX10-NEXT: v_readfirstlane_b32 s7, v7
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_usubsat_v2i128:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_sub_u32 s16, s0, s8
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s0, s[0:1], s[8:9]
+; GFX10PLUS-NEXT: s_subb_u32 s17, s1, s9
+; GFX10PLUS-NEXT: s_subb_u32 s18, s2, s10
+; GFX10PLUS-NEXT: s_subb_u32 s19, s3, s11
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[2:3], s[10:11]
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s0, s[2:3], s[10:11]
+; GFX10PLUS-NEXT: s_cselect_b32 s20, 1, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX10PLUS-NEXT: s_and_b32 s0, 1, s20
+; GFX10PLUS-NEXT: s_sub_u32 s2, s4, s12
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s4, s[4:5], s[12:13]
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
+; GFX10PLUS-NEXT: s_subb_u32 s1, s5, s13
+; GFX10PLUS-NEXT: s_subb_u32 s8, s6, s14
+; GFX10PLUS-NEXT: s_subb_u32 s3, s7, s15
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[6:7], s[14:15]
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s4, s[6:7], s[14:15]
+; GFX10PLUS-NEXT: s_cselect_b32 s0, 1, 0
+; GFX10PLUS-NEXT: s_and_b32 s0, 1, s0
+; GFX10PLUS-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX10PLUS-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, s16, 0, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, s18, 0, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, s19, 0, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_ne_u32_e64 s0, 0, v1
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, s17, 0, vcc_lo
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v4, s2, 0, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v5, s1, 0, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v6, s8, 0, s0
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v7, s3, 0, s0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v4
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s5, v5
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s6, v6
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s7, v7
+; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <2 x i128> @llvm.usub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
ret <2 x i128> %result
}
diff --git a/llvm/test/CodeGen/AMDGPU/build_vector.ll b/llvm/test/CodeGen/AMDGPU/build_vector.ll
index e19c8d527f226..b0e655342e513 100644
--- a/llvm/test/CodeGen/AMDGPU/build_vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/build_vector.ll
@@ -1,16 +1,20 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefixes=R600,ALL
-; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefixes=SI,GFX6,GFX678,ALL
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefixes=SI,GFX8,GFX678,ALL
-; RUN: llc < %s -mtriple=amdgcn-amd-amdpal -mcpu=gfx1030 -verify-machineinstrs | FileCheck %s --check-prefixes=GFX10,SI,ALL
+; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefixes=GFX6,GFX678,ALL
+; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefixes=GFX8,GFX678,ALL
+; RUN: llc < %s -mtriple=amdgcn-amd-amdpal -mcpu=gfx1030 -verify-machineinstrs | FileCheck %s --check-prefixes=GFX10,GFX1011,ALL
+; RUN: llc < %s -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -verify-machineinstrs | FileCheck %s --check-prefixes=GFX11,GFX1011,ALL
; ALL-LABEL: {{^}}build_vector2:
; R600: MOV
; R600: MOV
; R600-NOT: MOV
-; SI-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
-; SI-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
+; GFX678-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
+; GFX678-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
+; GFX1011-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
+; GFX1011-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
; GFX678: buffer_store_dwordx2 v[[[X]]:[[Y]]]
; GFX10: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX11: global_store_b64 v2, v[0:1], s[0:1]
define amdgpu_kernel void @build_vector2 (<2 x i32> addrspace(1)* %out) {
entry:
store <2 x i32> <i32 5, i32 6>, <2 x i32> addrspace(1)* %out
@@ -23,12 +27,17 @@ entry:
; R600: MOV
; R600: MOV
; R600-NOT: MOV
-; SI-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
-; SI-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
-; SI-DAG: v_mov_b32_e32 v[[Z:[0-9]]], 7
-; SI-DAG: v_mov_b32_e32 v[[W:[0-9]]], 8
+; GFX678-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
+; GFX678-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
+; GFX678-DAG: v_mov_b32_e32 v[[Z:[0-9]]], 7
+; GFX678-DAG: v_mov_b32_e32 v[[W:[0-9]]], 8
+; GFX1011-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
+; GFX1011-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
+; GFX1011-DAG: v_mov_b32_e32 v[[Z:[0-9]]], 7
+; GFX1011-DAG: v_mov_b32_e32 v[[W:[0-9]]], 8
; GFX678: buffer_store_dwordx4 v[[[X]]:[[W]]]
; GFX10: global_store_dwordx4 v4, v[0:3], s[0:1]
+; GFX11: global_store_b128 v4, v[0:3], s[0:1]
define amdgpu_kernel void @build_vector4 (<4 x i32> addrspace(1)* %out) {
entry:
store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> addrspace(1)* %out
@@ -44,10 +53,11 @@ entry:
; GFX678: v_mov_b32_e32 v0, 0x60005
; GFX678: s_waitcnt lgkmcnt(0)
; GFX678: buffer_store_dword v0, off, s[0:3], 0
-; GFX10: v_mov_b32_e32 v0, 0
-; GFX10: v_mov_b32_e32 v1, 0x60005
-; GFX10: s_waitcnt lgkmcnt(0)
+; GFX1011: v_mov_b32_e32 v0, 0
+; GFX1011: v_mov_b32_e32 v1, 0x60005
+; GFX1011: s_waitcnt lgkmcnt(0)
; GFX10: global_store_dword v0, v1, s[0:1]
+; GFX11: global_store_b32 v0, v1, s[0:1]
define amdgpu_kernel void @build_vector_v2i16 (<2 x i16> addrspace(1)* %out) {
entry:
store <2 x i16> <i16 5, i16 6>, <2 x i16> addrspace(1)* %out
@@ -73,12 +83,14 @@ entry:
; GFX8: s_or_b32 s4, s4, 0x50000
; GFX8: v_mov_b32_e32 v0, s4
; GFX8: buffer_store_dword v0, off, s[0:3], 0
-; GFX10: v_mov_b32_e32 v0, 0
-; GFX10: s_waitcnt lgkmcnt(0)
+; GFX1011: v_mov_b32_e32 v0, 0
+; GFX1011: s_waitcnt lgkmcnt(0)
; GFX10: s_lshr_b32 s2, s2, 16
; GFX10: s_pack_ll_b32_b16 s2, s2, 5
-; GFX10: v_mov_b32_e32 v1, s2
+; GFX11: s_pack_hl_b32_b16 s2, s2, 5
+; GFX1011: v_mov_b32_e32 v1, s2
; GFX10: global_store_dword v0, v1, s[0:1]
+; GFX11: global_store_b32 v0, v1, s[0:1]
define amdgpu_kernel void @build_vector_v2i16_trunc (<2 x i16> addrspace(1)* %out, i32 %a) {
%srl = lshr i32 %a, 16
%trunc = trunc i32 %srl to i16
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