[PATCH] D124192: [AMDGPU] Callee must always spill writelane VGPRs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:102
+      auto Spill = MFI->getSGPRToVGPRSpills(NewFI).front();
+      MFI->addToWWMVGPRs(MF, Spill.VGPR);
+
----------------
cdevadas wrote:
> arsenm wrote:
> > Why is anything being added to WWM registers here?
> This function picks a new VGPR for FP/BP spilling and the actual spilling happens at emitPrologue/emitEpilogue.
> We should add them to WWMVGPRs (renamed from 'LaneVGPRs' after Nicolai's suggestion) that track all whole wave VGPRs and their FIs.
But this case uses an ordinary mov to copy to VGPR and spills directly to memory, not with writelane. We currently don't try to spill into a lane (although we could/should, at least merging the FP and BP into one slot)


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  https://reviews.llvm.org/D124192/new/

https://reviews.llvm.org/D124192