[PATCH] D128606: [AArch64][DAGCombiner] Swap the operations of logical operation AND to match movprfx

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

Is this optimisation valid? The merging SVE intrinsics have strict rules about what happens to inactive lanes. For the `llvm.aarch64.sve.and` the inactive lanes are set to the matching lanes of the first operand.  This means that the inactive lanes of the second operand play no role in the operation and thus the example in `and_i64_zero_comm` is not a `zeroing and`.

However, given the inactive lanes of the second operand play no role, this effectively means the `select` is redundant and can be optimised away as an instcombine before it gets to code generation.  So I guess the question is whether you are seeing this issue in real code and thus it's worth implementing the instcombine.


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  https://reviews.llvm.org/D128606/new/

https://reviews.llvm.org/D128606