[PATCH] D128570: [ISel] Round down mask bit when merge undef(s) for DAG combine

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

Please add test coverage in APIntTest.cpp



================
Comment at: llvm/include/llvm/ADT/APInt.h:2252
 /// TODO: Do we need a mode where all bits must be set when merging down?
-APInt ScaleBitMask(const APInt &A, unsigned NewBitWidth);
+APInt ScaleBitMask(const APInt &A, unsigned NewBitWidth, bool Down = false);
 } // namespace APIntOps
----------------
Yes, 'down' in the TODO meant when reducing the number of bits - maybe 'MatchAllBits' would be better? Current behaviour is 'MatchAnyBits'.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128570/new/

https://reviews.llvm.org/D128570