[PATCH] D127642: [RISCV] Fixing undefined physical register issue when subreg liveness tracking enabled.

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

We do this (adding implicit super register operands) in AMDGPU too, but eventually they start getting in the way of other optimizations. I'd really like it if we could agree on another way to fix the physical subreg liveness problem. See: https://discourse.llvm.org/t/physical-subregister-liveness/5994


Repository:
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https://reviews.llvm.org/D127642