[PATCH] D128570: [ISel] Round down mask bit when merge undef(s) for DAG combine

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/include/llvm/ADT/APInt.h:2251
 ///
 /// TODO: Do we need a mode where all bits must be set when merging down?
+APInt ScaleBitMask(const APInt &A, unsigned NewBitWidth, bool Down = false);
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This comment uses the word "down" as well, but to mean the number of bits is decreasing.  I believe this patch is implementing this TODO.


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  https://reviews.llvm.org/D128570/new/

https://reviews.llvm.org/D128570