[PATCH] D128703: [PowerPC] Improve getNormalLoadInput to reach more splat load opportunities

[Ting Wang via Phabricator via llvm-commits]

tingwang created this revision.
tingwang added reviewers: shchenz, nemanjai, PowerPC.
tingwang added a project: LLVM.
Herald added subscribers: kbarton, hiraditya.
Herald added a project: All.
tingwang requested review of this revision.
Herald added a subscriber: llvm-commits.

There are straight forward splat load opportunities blocked by getNormalLoadInput(), since those cases involve consecutive bitcasts. Improve by looking through bitcasts.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D128703

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/load-and-splat.ll


Index: llvm/test/CodeGen/PowerPC/load-and-splat.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/load-and-splat.ll
+++ llvm/test/CodeGen/PowerPC/load-and-splat.ll
@@ -1322,3 +1322,82 @@
   %vecinit5 = shufflevector <2 x double> %vecinit, <2 x double> poison, <2 x i32> zeroinitializer
   ret <2 x double> %vecinit5
 }
+
+define <4 x i32> @test_splatW(<8 x i16>* %ptr) {
+; P9-LABEL: test_splatW:
+; P9:       # %bb.0: # %entry
+; P9-NEXT:    lxvwsx v2, 0, r3
+; P9-NEXT:    blr
+;
+; P8-LABEL: test_splatW:
+; P8:       # %bb.0: # %entry
+; P8-NEXT:    lxvd2x vs0, 0, r3
+; P8-NEXT:    xxswapd v2, vs0
+; P8-NEXT:    xxspltw v2, v2, 3
+; P8-NEXT:    blr
+;
+; P7-LABEL: test_splatW:
+; P7:       # %bb.0: # %entry
+; P7-NEXT:    lxvw4x vs0, 0, r3
+; P7-NEXT:    xxspltw v2, vs0, 0
+; P7-NEXT:    blr
+;
+; P9-AIX32-LABEL: test_splatW:
+; P9-AIX32:       # %bb.0: # %entry
+; P9-AIX32-NEXT:    lxvwsx v2, 0, r3
+; P9-AIX32-NEXT:    blr
+;
+; P8-AIX32-LABEL: test_splatW:
+; P8-AIX32:       # %bb.0: # %entry
+; P8-AIX32-NEXT:    lxvw4x vs0, 0, r3
+; P8-AIX32-NEXT:    xxspltw v2, vs0, 0
+; P8-AIX32-NEXT:    blr
+;
+; P7-AIX32-LABEL: test_splatW:
+; P7-AIX32:       # %bb.0: # %entry
+; P7-AIX32-NEXT:    lxvw4x vs0, 0, r3
+; P7-AIX32-NEXT:    xxspltw v2, vs0, 0
+; P7-AIX32-NEXT:    blr
+entry:
+  %0 = load <8 x i16>, <8 x i16>* %ptr, align 16
+  %1 = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
+  %2 = bitcast<8 x i16> %1 to <4 x i32>
+  ret <4 x i32> %2
+}
+
+define <4 x i32> @test_splatD(<8 x i16>* %ptr) {
+; P9-LABEL: test_splatD:
+; P9:       # %bb.0: # %entry
+; P9-NEXT:    lxvdsx v2, 0, r3
+; P9-NEXT:    blr
+;
+; P8-LABEL: test_splatD:
+; P8:       # %bb.0: # %entry
+; P8-NEXT:    lxvdsx v2, 0, r3
+; P8-NEXT:    blr
+;
+; P7-LABEL: test_splatD:
+; P7:       # %bb.0: # %entry
+; P7-NEXT:    lxvdsx v2, 0, r3
+; P7-NEXT:    blr
+;
+; P9-AIX32-LABEL: test_splatD:
+; P9-AIX32:       # %bb.0: # %entry
+; P9-AIX32-NEXT:    lxvdsx v2, 0, r3
+; P9-AIX32-NEXT:    blr
+;
+; P8-AIX32-LABEL: test_splatD:
+; P8-AIX32:       # %bb.0: # %entry
+; P8-AIX32-NEXT:    lxvdsx v2, 0, r3
+; P8-AIX32-NEXT:    blr
+;
+; P7-AIX32-LABEL: test_splatD:
+; P7-AIX32:       # %bb.0: # %entry
+; P7-AIX32-NEXT:    lxvdsx v2, 0, r3
+; P7-AIX32-NEXT:    blr
+entry:
+  %0 = load <8 x i16>, <8 x i16>* %ptr, align 16
+  %1 = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
+  %2 = bitcast<8 x i16> %1 to <4 x i32>
+  ret <4 x i32> %2
+}
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -9073,7 +9073,7 @@
 
 static const SDValue *getNormalLoadInput(const SDValue &Op, bool &IsPermuted) {
   const SDValue *InputLoad = &Op;
-  if (InputLoad->getOpcode() == ISD::BITCAST)
+  while (InputLoad->getOpcode() == ISD::BITCAST)
     InputLoad = &InputLoad->getOperand(0);
   if (InputLoad->getOpcode() == ISD::SCALAR_TO_VECTOR ||
       InputLoad->getOpcode() == PPCISD::SCALAR_TO_VECTOR_PERMUTED) {


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