[PATCH] D128682: [AMDGPU] gfx11 CodeGen for new DPP instructions

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp:145
 
-int GCNDPPCombine::getDPPOp(unsigned Op, bool IsShrinkable) const {
+int GCNDPPCombine::getDPPOp(unsigned Op, bool HasVOP3DPP,
+                            bool IsShrinkable) const {
----------------
No need to pass HasVOP3DPP, you have ST available here and it is a trivial getter.


================
Comment at: llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp:148
   auto DPP32 = AMDGPU::getDPPOp32(Op);
+  auto DPP64 = AMDGPU::getDPPOp64(Op);
   if (IsShrinkable) {
----------------
You could search for DPP4 opcode only is HasVOP3DPP.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128682/new/

https://reviews.llvm.org/D128682