[PATCH] D124564: [MachineCombiner, AArch64] Add a new pattern A-(B+C) => (A-B)-C to reduce latency

Mon Jun 27 15:25:42 PDT 2022

Carrot added a comment.

In D124564#3610891 <https://reviews.llvm.org/D124564#3610891>, @dmgreen wrote:

> Oh yeah, I see. The way MachineCombiner's logic is held in target independent files for target patterns always trips me up. To check - this doesn't need the changes from D125588 <https://reviews.llvm.org/D125588> now? It works stand-alone?

This optimization doesn't depend on D125588 <https://reviews.llvm.org/D125588>, it was the test case. In the original test case there are several operands come from COPY directly, and wrong latency is computed for them. In current version I added several instructions so no operands of SUB/ADD come from COPY instructions.

> The mir tests are good - thanks for explaining them well. Can you add a test for a extra uses of the Add.

Done.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124564/new/

https://reviews.llvm.org/D124564