[llvm] 9afa5b8 - [RISCV] Add tests for (load (add X, [2048, 4094])). NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-06-27T13:42:57-07:00
New Revision: 9afa5b8da2282ffaf21288d4bf2fdf19ea182dbb

URL: https://github.com/llvm/llvm-project/commit/9afa5b8da2282ffaf21288d4bf2fdf19ea182dbb
DIFF: https://github.com/llvm/llvm-project/commit/9afa5b8da2282ffaf21288d4bf2fdf19ea182dbb.diff

LOG: [RISCV] Add tests for (load (add X, [2048,4094])). NFC

Offsets in the range [-4095,-2049] or [2048, 4094] are split into
two ADDIs. One of the ADDIs will be folded into the load/store
immediate through an post-isel peephole.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/mem.ll
    llvm/test/CodeGen/RISCV/mem64.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/mem.ll b/llvm/test/CodeGen/RISCV/mem.ll
index 833496705a701..b05eb818e3591 100644
--- a/llvm/test/CodeGen/RISCV/mem.ll
+++ b/llvm/test/CodeGen/RISCV/mem.ll
@@ -199,6 +199,41 @@ define dso_local i32 @lw_sw_constant(i32 %a) nounwind {
   ret i32 %2
 }
 
+define i32 @lw_near_local(i32* %a)  {
+; RV32I-LABEL: lw_near_local:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a0, a0, 2047
+; RV32I-NEXT:    lw a0, 5(a0)
+; RV32I-NEXT:    ret
+  %1 = getelementptr inbounds i32, i32* %a, i64 513
+  %2 = load volatile i32, i32* %1
+  ret i32 %2
+}
+
+define void @st_near_local(i32* %a, i32 %b)  {
+; RV32I-LABEL: st_near_local:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a0, a0, 2047
+; RV32I-NEXT:    sw a1, 5(a0)
+; RV32I-NEXT:    ret
+  %1 = getelementptr inbounds i32, i32* %a, i64 513
+  store i32 %b, i32* %1
+  ret void
+}
+
+define i32 @lw_sw_near_local(i32* %a, i32 %b)  {
+; RV32I-LABEL: lw_sw_near_local:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a2, a0, 2047
+; RV32I-NEXT:    lw a0, 5(a2)
+; RV32I-NEXT:    sw a1, 5(a2)
+; RV32I-NEXT:    ret
+  %1 = getelementptr inbounds i32, i32* %a, i64 513
+  %2 = load volatile i32, i32* %1
+  store i32 %b, i32* %1
+  ret i32 %2
+}
+
 define i32 @lw_far_local(i32* %a)  {
 ; RV32I-LABEL: lw_far_local:
 ; RV32I:       # %bb.0:

diff  --git a/llvm/test/CodeGen/RISCV/mem64.ll b/llvm/test/CodeGen/RISCV/mem64.ll
index 10255f4f7f0c0..018a9565f562e 100644
--- a/llvm/test/CodeGen/RISCV/mem64.ll
+++ b/llvm/test/CodeGen/RISCV/mem64.ll
@@ -229,6 +229,41 @@ define dso_local i64 @ld_sd_global(i64 %a) nounwind {
   ret i64 %1
 }
 
+define i64 @lw_near_local(i64* %a)  {
+; RV64I-LABEL: lw_near_local:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a0, a0, 2047
+; RV64I-NEXT:    ld a0, 9(a0)
+; RV64I-NEXT:    ret
+  %1 = getelementptr inbounds i64, i64* %a, i64 257
+  %2 = load volatile i64, i64* %1
+  ret i64 %2
+}
+
+define void @st_near_local(i64* %a, i64 %b)  {
+; RV64I-LABEL: st_near_local:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a0, a0, 2047
+; RV64I-NEXT:    sd a1, 9(a0)
+; RV64I-NEXT:    ret
+  %1 = getelementptr inbounds i64, i64* %a, i64 257
+  store i64 %b, i64* %1
+  ret void
+}
+
+define i64 @lw_sw_near_local(i64* %a, i64 %b)  {
+; RV64I-LABEL: lw_sw_near_local:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a2, a0, 2047
+; RV64I-NEXT:    ld a0, 9(a2)
+; RV64I-NEXT:    sd a1, 9(a2)
+; RV64I-NEXT:    ret
+  %1 = getelementptr inbounds i64, i64* %a, i64 257
+  %2 = load volatile i64, i64* %1
+  store i64 %b, i64* %1
+  ret i64 %2
+}
+
 define i64 @lw_far_local(i64* %a)  {
 ; RV64I-LABEL: lw_far_local:
 ; RV64I:       # %bb.0: