[llvm] 97ed2fb - MIR: Fix parse error on empty CustomRegMask

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2022-06-27T08:50:35-04:00
New Revision: 97ed2fbc5f646a4118eccd12de588bb344e25c58

URL: https://github.com/llvm/llvm-project/commit/97ed2fbc5f646a4118eccd12de588bb344e25c58
DIFF: https://github.com/llvm/llvm-project/commit/97ed2fbc5f646a4118eccd12de588bb344e25c58.diff

LOG: MIR: Fix parse error on empty CustomRegMask

Added: 
    llvm/test/CodeGen/MIR/AMDGPU/empty-custom-regmask.mir

Modified: 
    llvm/lib/CodeGen/MIRParser/MIParser.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index 62ce62f72334b..40ae7053ea09c 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -2707,19 +2707,19 @@ bool MIParser::parseCustomRegisterMaskOperand(MachineOperand &Dest) {
     return true;
 
   uint32_t *Mask = MF.allocateRegMask();
-  while (true) {
-    if (Token.isNot(MIToken::NamedRegister))
-      return error("expected a named register");
-    Register Reg;
-    if (parseNamedRegister(Reg))
-      return true;
-    lex();
-    Mask[Reg / 32] |= 1U << (Reg % 32);
+  do {
+    if (Token.isNot(MIToken::rparen)) {
+      if (Token.isNot(MIToken::NamedRegister))
+        return error("expected a named register");
+      Register Reg;
+      if (parseNamedRegister(Reg))
+        return true;
+      lex();
+      Mask[Reg / 32] |= 1U << (Reg % 32);
+    }
+
     // TODO: Report an error if the same register is used more than once.
-    if (Token.isNot(MIToken::comma))
-      break;
-    lex();
-  }
+  } while (consumeIfPresent(MIToken::comma));
 
   if (expectAndConsume(MIToken::rparen))
     return true;

diff  --git a/llvm/test/CodeGen/MIR/AMDGPU/empty-custom-regmask.mir b/llvm/test/CodeGen/MIR/AMDGPU/empty-custom-regmask.mir
new file mode 100644
index 0000000000000..8dfc3ddc427f6
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/AMDGPU/empty-custom-regmask.mir
@@ -0,0 +1,18 @@
+# RUN: llc -march=amdgcn -run-pass=none -o - %s | FileCheck %s
+
+# Make sure there's no parse error on empty CustomRegMask or trailing comma
+
+# CHECK: $sgpr30_sgpr31 = SI_CALL %0, 0, CustomRegMask()
+# CHECK: $sgpr30_sgpr31 = SI_CALL %0, 0, CustomRegMask($vgpr0)
+
+---
+name: func
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $sgpr8_sgpr9
+    %0:sreg_64_xexec = COPY $sgpr8_sgpr9
+    $sgpr30_sgpr31 = SI_CALL %0, 0, CustomRegMask()
+    $sgpr30_sgpr31 = SI_CALL %0, 0, CustomRegMask($vgpr0,)
+    S_ENDPGM 0
+...