[llvm] 5e944e9 - [RISCV] Refactor SelectAddrRegImm to not depend on SelectBaseAddr.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 26 11:14:50 PDT 2022
Author: Craig Topper
Date: 2022-06-26T11:11:41-07:00
New Revision: 5e944e9eb72aa7ea7fe2542d18813a646b3933d1
URL: https://github.com/llvm/llvm-project/commit/5e944e9eb72aa7ea7fe2542d18813a646b3933d1
DIFF: https://github.com/llvm/llvm-project/commit/5e944e9eb72aa7ea7fe2542d18813a646b3933d1.diff
LOG: [RISCV] Refactor SelectAddrRegImm to not depend on SelectBaseAddr.
SelectBaseAddr was a minor convenience to use since it already'
existed for vector load/store. D128187 is going to remove the other
uses of SelectBaseAddr so it has less reason to exist.
This patch removes the dependency on SelectBaseAddr and adds a new
SelectAddrFrameIndex to share some code with SelectFrameAddrRegImm.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 75f5f392a5bf1..92a547c542b1b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1790,15 +1790,23 @@ bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(
return true;
}
-// Select a frame index and an optional immediate offset from an ADD or OR.
-bool RISCVDAGToDAGISel::SelectFrameAddrRegImm(SDValue Addr, SDValue &Base,
- SDValue &Offset) {
+bool RISCVDAGToDAGISel::SelectAddrFrameIndex(SDValue Addr, SDValue &Base,
+ SDValue &Offset) {
if (auto *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), Subtarget->getXLenVT());
Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Subtarget->getXLenVT());
return true;
}
+ return false;
+}
+
+// Select a frame index and an optional immediate offset from an ADD or OR.
+bool RISCVDAGToDAGISel::SelectFrameAddrRegImm(SDValue Addr, SDValue &Base,
+ SDValue &Offset) {
+ if (SelectAddrFrameIndex(Addr, Base, Offset))
+ return true;
+
if (!CurDAG->isBaseWithConstantOffset(Addr))
return false;
@@ -1828,17 +1836,25 @@ bool RISCVDAGToDAGISel::SelectBaseAddr(SDValue Addr, SDValue &Base) {
bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
SDValue &Offset) {
+ if (SelectAddrFrameIndex(Addr, Base, Offset))
+ return true;
+
if (CurDAG->isBaseWithConstantOffset(Addr)) {
auto *CN = cast<ConstantSDNode>(Addr.getOperand(1));
if (isInt<12>(CN->getSExtValue())) {
+ Base = Addr.getOperand(0);
+ if (auto *FIN = dyn_cast<FrameIndexSDNode>(Base))
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(),
+ Subtarget->getXLenVT());
Offset = CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(Addr),
Subtarget->getXLenVT());
- return SelectBaseAddr(Addr.getOperand(0), Base);
+ return true;
}
}
+ Base = Addr;
Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Subtarget->getXLenVT());
- return SelectBaseAddr(Addr, Base);
+ return true;
}
bool RISCVDAGToDAGISel::selectShiftMask(SDValue N, unsigned ShiftWidth,
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
index d4eadb5f1b3ec..b50927cfcca53 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -45,6 +45,7 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
std::vector<SDValue> &OutOps) override;
+ bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset);
bool SelectFrameAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset);
bool SelectBaseAddr(SDValue Addr, SDValue &Base);
bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset);
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