[PATCH] D124564: [MachineCombiner, AArch64] Add a new pattern A-(B+C) => (A-B)-C to reduce latency

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

> I think there are more similar useful patterns, but I encountered this pattern only. We can add other patterns when we have tests.
>
> This pattern does look like existing reassociate. The difference is its operations are not commutable, so it can't be handled by existing reassociate logic.

OK. I agree these are different to the existing reassociate patterns, but if this is worth adding we might want to look into improving those too. We needn't do that in this patch though, we can look at that separately.

> It is already marked as MustReduceDepth in function getCombinerObjective.

Oh yeah, I see. The way MachineCombiner's logic is held in target independent files for target patterns always trips me up. To check - this doesn't need the changes from D125588 <https://reviews.llvm.org/D125588> now? It works stand-alone?

The mir tests are good - thanks for explaining them well. Can you add a test for a extra uses of the Add.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124564/new/

https://reviews.llvm.org/D124564