[PATCH] D128613: Add explicit index type for llvm.vector.extract
Liao Chunyu via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 26 08:31:44 PDT 2022
liaolucy created this revision.
liaolucy added reviewers: craig.topper, joechrisellis, khchen.
Herald added subscribers: StephenFan, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, jocewei, PkmX, arphaman, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb.
Herald added a project: All.
liaolucy requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, jdoerfert, MaskRay.
Herald added projects: clang, LLVM.
Without this patch, we get: llvm.experimental.vector.extract.nxv.nxv
Whereas with the patch we get:
RV32, the intrinsic name is: llvm.experimental.vector.extract.nxv.nxv.i32
RV64, the intrinsic name is: llvm.experimental.vector.extract.nxv.nxv.i64
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D128613
Files:
clang/include/clang/Basic/riscv_vector.td
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vget.c
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlmul.c
clang/test/CodeGen/RISCV/rvv-intrinsics/vget.c
clang/test/CodeGen/RISCV/rvv-intrinsics/vlmul.c
clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
clang/test/CodeGen/aarch64-sve-vls-arith-ops.c
clang/test/CodeGen/aarch64-sve-vls-bitwise-ops.c
clang/test/CodeGen/aarch64-sve-vls-compare-ops.c
clang/test/CodeGen/aarch64-sve-vls-shift-ops.c
clang/test/CodeGen/aarch64-sve-vls-subscript-ops.c
clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_get_neonq.c
clang/test/CodeGen/attr-arm-sve-vector-bits-bitcast.c
clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
clang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
llvm/include/llvm/IR/IRBuilder.h
llvm/include/llvm/IR/Intrinsics.td
llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll
llvm/test/Transforms/InstCombine/canonicalize-vector-extract.ll
llvm/test/Transforms/InstSimplify/extract-vector.ll
llvm/test/Transforms/InstSimplify/insert-vector.ll
llvm/test/Transforms/InterleavedAccess/AArch64/sve-interleaved-accesses.ll
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