[llvm] 341e03f - X86: Regenerate test checks

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2022-06-25T09:24:53-04:00
New Revision: 341e03f9f3c0e2abc975be39bd9862dd0f68ad8b

URL: https://github.com/llvm/llvm-project/commit/341e03f9f3c0e2abc975be39bd9862dd0f68ad8b
DIFF: https://github.com/llvm/llvm-project/commit/341e03f9f3c0e2abc975be39bd9862dd0f68ad8b.diff

LOG: X86: Regenerate test checks

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/unfoldMemoryOperand.mir

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/unfoldMemoryOperand.mir b/llvm/test/CodeGen/X86/unfoldMemoryOperand.mir
index aea7170ee8953..e5b81ebecc6a4 100644
--- a/llvm/test/CodeGen/X86/unfoldMemoryOperand.mir
+++ b/llvm/test/CodeGen/X86/unfoldMemoryOperand.mir
@@ -83,23 +83,27 @@ machineFunctionInfo: {}
 body:             |
   ; CHECK-LABEL: name: _Z3foov
   ; CHECK: bb.0 (%ir-block.0):
-  ; CHECK:   successors: %bb.2(0x80000000)
-  ; CHECK:   renamable $eax = MOV32r0 implicit-def dead $eflags
-  ; CHECK:   renamable $rcx = MOV64ri32 -4096
-  ; CHECK:   [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 -4096
-  ; CHECK:   [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm $rip, 1, $noreg, @y, $noreg :: (dereferenceable load (s64) from @y, !tbaa !3)
-  ; CHECK:   JMP_1 %bb.2
-  ; CHECK: bb.1 (%ir-block.4):
-  ; CHECK:   RET 0
-  ; CHECK: bb.2 (%ir-block.5):
-  ; CHECK:   successors: %bb.1(0x04000000), %bb.2(0x7c000000)
-  ; CHECK:   liveins: $eax, $rcx
-  ; CHECK:   CMP64ri32 [[MOV64rm]], @x, implicit-def $eflags
-  ; CHECK:   renamable $al = SETCCr 4, implicit killed $eflags, implicit killed $eax, implicit-def $eax
-  ; CHECK:   MOV32mr renamable $rcx, 1, $noreg, @z + 4096, $noreg, renamable $eax :: (store (s32) into %ir.scevgep, !tbaa !7)
-  ; CHECK:   renamable $rcx = ADD64ri8 killed renamable $rcx, 4, implicit-def $eflags
-  ; CHECK:   JCC_1 %bb.1, 4, implicit killed $eflags
-  ; CHECK:   JMP_1 %bb.2
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   renamable $eax = MOV32r0 implicit-def dead $eflags
+  ; CHECK-NEXT:   renamable $rcx = MOV64ri32 -4096
+  ; CHECK-NEXT:   [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 -4096
+  ; CHECK-NEXT:   [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm $rip, 1, $noreg, @y, $noreg :: (dereferenceable load (s64) from @y, !tbaa !3)
+  ; CHECK-NEXT:   JMP_1 %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1 (%ir-block.4):
+  ; CHECK-NEXT:   RET 0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2 (%ir-block.5):
+  ; CHECK-NEXT:   successors: %bb.1(0x04000000), %bb.2(0x7c000000)
+  ; CHECK-NEXT:   liveins: $eax, $rcx
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   CMP64ri32 [[MOV64rm]], @x, implicit-def $eflags
+  ; CHECK-NEXT:   renamable $al = SETCCr 4, implicit killed $eflags, implicit killed $eax, implicit-def $eax
+  ; CHECK-NEXT:   MOV32mr renamable $rcx, 1, $noreg, @z + 4096, $noreg, renamable $eax :: (store (s32) into %ir.scevgep, !tbaa !7)
+  ; CHECK-NEXT:   renamable $rcx = ADD64ri8 killed renamable $rcx, 4, implicit-def $eflags
+  ; CHECK-NEXT:   JCC_1 %bb.1, 4, implicit killed $eflags
+  ; CHECK-NEXT:   JMP_1 %bb.2
   bb.0 (%ir-block.0):
     successors: %bb.2(0x80000000)
     renamable $eax = MOV32r0 implicit-def dead $eflags