[PATCH] D128583: CodeGen: Remove AliasAnalysis from regalloc

[Matt Arsenault via Phabricator via llvm-commits]

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This was stored in LiveIntervals, but not actually used for anything
related to LiveIntervals. It was only used in one check for if a load
instruction is rematerializable. I also don't think this was entirely
correct, since it was implicitly assuming constant loads are also
dereferenceable.

      

Remove this and rely only on the invariant+dereferenceable flags in
the memory operand. Set the flag based on the AA query upfront. This
should have the same net benefit, but has the possible disadvantage of
making this AA query nonlazy.

      

Preserve the behavior of assuming pointsToConstantMemory implying
dereferenceable for now, but maybe this should be changed.


https://reviews.llvm.org/D128583

Files:
  llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
  llvm/include/llvm/CodeGen/LiveIntervals.h
  llvm/include/llvm/CodeGen/LiveRangeEdit.h
  llvm/include/llvm/CodeGen/MachineInstr.h
  llvm/include/llvm/CodeGen/SelectionDAG.h
  llvm/include/llvm/CodeGen/TargetInstrInfo.h
  llvm/lib/CodeGen/CalcSpillWeights.cpp
  llvm/lib/CodeGen/EarlyIfConversion.cpp
  llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
  llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
  llvm/lib/CodeGen/InlineSpiller.cpp
  llvm/lib/CodeGen/LiveIntervals.cpp
  llvm/lib/CodeGen/LiveRangeEdit.cpp
  llvm/lib/CodeGen/MLRegallocEvictAdvisor.cpp
  llvm/lib/CodeGen/MachineCSE.cpp
  llvm/lib/CodeGen/MachineInstr.cpp
  llvm/lib/CodeGen/MachineLICM.cpp
  llvm/lib/CodeGen/MachinePipeliner.cpp
  llvm/lib/CodeGen/RegAllocBasic.cpp
  llvm/lib/CodeGen/RegAllocGreedy.cpp
  llvm/lib/CodeGen/RegAllocGreedy.h
  llvm/lib/CodeGen/RegAllocScore.cpp
  llvm/lib/CodeGen/RegAllocScore.h
  llvm/lib/CodeGen/RegisterCoalescer.cpp
  llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/CodeGen/SplitKit.cpp
  llvm/lib/CodeGen/SplitKit.h
  llvm/lib/CodeGen/TargetInstrInfo.cpp
  llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
  llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.h
  llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.h
  llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.h
  llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h
  llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/lib/Target/X86/X86InstrInfo.h
  llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll
  llvm/test/CodeGen/AArch64/arm64-memcpy-inline.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll
  llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll
  llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
  llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
  llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll
  llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
  llvm/test/CodeGen/X86/unfoldMemoryOperand.mir

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