[PATCH] D128572: [LoongArch] Add codegen support for division operations

Sat Jun 25 01:41:44 PDT 2022

xen0n added a comment.

In D128572#3609943 <https://reviews.llvm.org/D128572#3609943>, @SixWeining wrote:

> In D128572#3609897 <https://reviews.llvm.org/D128572#3609897>, @xen0n wrote:
>
>> Trapping division/modulus operations are signatures of MIPS codegen, and indeed here the trapping-by-default behavior and the flag seem to come from MIPS. However, as division-by-zero in LLVM IR is undefined behavior, why can't we just omit the trapping behavior altogether (and match RISCV in this regard), or at least disable the trapping by default?
>
> Good question! This is  what I have ever thought. In fact I don't know why mips needs to check zero-divide by default. riscv and aarch64 do not check and I'm not sure it is because their ISAs define zero-divide having an fixed result while Mips and LoongArch do not.
> Currently the upstramed gcc checks zero-divide by default, so here I do as it to keep consistent.

Might be better to just flip the switch on gcc upstream. @xry111 has kindly forwarded my comment to the Loongson GCC issue tracker <https://github.com/loongson/gcc/issues/107> so we could continue discussion there regarding gcc.

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https://reviews.llvm.org/D128572