[PATCH] D123265: [RISCV] Extend the Merge Base Offset pass to handle AUIPC+ADDI

[Luís Marques via Phabricator via llvm-commits]

luismarques updated this revision to Diff 439925.
luismarques added a comment.

- Rebase
- Handle non-zero offsets in tail load/store instructions


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123265/new/

https://reviews.llvm.org/D123265

Files:
  llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
  llvm/test/CodeGen/RISCV/codemodel-lowering.ll
  llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
  llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll

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