[llvm] f1b1bcd - [RISCV] Replace two calls to getMinRVVVectorSizeInBits with getRealMinVLen [nfc]

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2022-06-24T12:07:33-07:00
New Revision: f1b1bcdbd4b405876577693f402d1787ca6a2985

URL: https://github.com/llvm/llvm-project/commit/f1b1bcdbd4b405876577693f402d1787ca6a2985
DIFF: https://github.com/llvm/llvm-project/commit/f1b1bcdbd4b405876577693f402d1787ca6a2985.diff

LOG: [RISCV] Replace two calls to getMinRVVVectorSizeInBits with getRealMinVLen [nfc]

This doesn't change behavior, it just makes it slightly more obvious what's
going on.  Note that getRealMinVLen is always >= getMinRVVVectorSizeInBits.

The first case is a bit tricky, as you have to know that
getMinRVVVectorSizeInBits returns 0 when not set, and thus is equivalent
to the else value clause.  The new code structure makes it more obvious we
return 0 unless using RVV for fixed length vectors.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index e35e17aa3877..8092b9c96f49 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -154,7 +154,7 @@ RISCVTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
     return TypeSize::getFixed(ST->getXLen());
   case TargetTransformInfo::RGK_FixedWidthVector:
     return TypeSize::getFixed(
-        ST->hasVInstructions() ? LMUL * ST->getMinRVVVectorSizeInBits() : 0);
+        ST->useRVVForFixedLengthVectors() ? LMUL * ST->getRealMinVLen() : 0);
   case TargetTransformInfo::RGK_ScalableVector:
     return TypeSize::getScalable(
         ST->hasVInstructions() ? LMUL * RISCV::RVVBitsPerBlock : 0);
@@ -466,7 +466,7 @@ unsigned RISCVTTIImpl::getRegUsageForType(Type *Ty) {
       return divideCeil(Size.getKnownMinValue(), RISCV::RVVBitsPerBlock);
 
     if (ST->useRVVForFixedLengthVectors())
-      return divideCeil(Size, ST->getMinRVVVectorSizeInBits());
+      return divideCeil(Size, ST->getRealMinVLen());
   }
 
   return BaseT::getRegUsageForType(Ty);