[PATCH] D128546: [GlobalISel] Do not crash on widening vector result

[Serge Pavlov via Phabricator via llvm-commits]

sepavloff created this revision.
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Function buildCopyToRegs did not handle properly the case when it should
make wider vector result. It happened, for example, in a function that
returns value of type <2 x f32>, which should be widen to <4 x f32> to
fit XMM register on X86. The function eventually calls
MachineIRBuilder::buildUnmerge, which does not expect that only one
destination register is specified.

Now this case is treated specifically in buildCopyToRegs.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D128546

Files:
  llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
  llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator.ll


Index: llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator.ll
===================================================================
--- llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator.ll
+++ llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator.ll
@@ -364,3 +364,16 @@
   %res = urem i64 %arg1, %arg2
   ret i64 %res
 }
+
+define <2 x float> @test_const_v2f32() {
+  ; CHECK-LABEL: name: test_const_v2f32
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+  ; CHECK-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
+  ; CHECK-NEXT:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x s32>)
+  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; CHECK-NEXT:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[DEF]](s32), [[DEF]](s32)
+  ; CHECK-NEXT:   $xmm0 = COPY [[BUILD_VECTOR1]](<4 x s32>)
+  ; CHECK-NEXT:   RET 0, implicit $xmm0
+  ret <2 x float><float 1.0, float 1.0>
+}
Index: llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
===================================================================
--- llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -489,6 +489,15 @@
     return;
   }
 
+  if (SrcTy.isVector() && PartTy.isVector() &&
+      PartTy.getScalarSizeInBits() == SrcTy.getScalarSizeInBits() &&
+      SrcTy.getNumElements() < PartTy.getNumElements()) {
+    // A coercion like: v2f32 -> v4f32.
+    Register DstReg = DstRegs.front();
+    B.buildPadVectorWithUndefElements(DstReg, SrcReg);
+    return;
+  }
+
   LLT GCDTy = getGCDType(SrcTy, PartTy);
   if (GCDTy == PartTy) {
     // If this already evenly divisible, we can create a simple unmerge.


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