[PATCH] D128500: [RISCV] Change how we isel (add X, [-4096, -2049]) or (add X, [2048,4095]).

[Craig Topper via Phabricator via llvm-commits]

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We currently split the immediate almost equally between two addis.
If the immediate is odd, it won't be split exactly equal.

This patch instead gives one addi an immediate of 2047 or -2048 and the
other getsthe remainder. If the original immediate is near -2049 or 2048,
this might allow the use of c.addi for the addi that receives the
smaller immediate.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D128500

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/test/CodeGen/RISCV/add-imm.ll
  llvm/test/CodeGen/RISCV/addimm-mulimm.ll
  llvm/test/CodeGen/RISCV/xaluo.ll

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