[PATCH] D128427: [LoongArch] Add codegen support for load/store operations

[Ray Wang via Phabricator via llvm-commits]

wangleiat added inline comments.


================
Comment at: llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp:123
+        SDValue(DAG.getMachineNode(LoongArch::PCALAU12I, DL, Ty, GA), 0);
+    SDValue Addr = SDValue(DAG.getMachineNode(ADDIOp, DL, Ty, AddrHi, GA), 0);
+    return Addr;
----------------
xen0n wrote:
> Because `pcalau12i` always produces results with the lower 12 bits clean, isn't `ori` more suitable for concatenating the lower bits?
The linker will corrects the `pcalau12i` instruction based on whether bit 12 is 1.
The advantage of this is that there is a chance to combine the `addi.{d,w}` instruction with the load/store instruction.

example:
```
pcalau12i $a1, %pc_hi20(G)
addi.d $a2, $a1, %pc_lo12(G)
ld.w $a1, $a2, 0
=>
pcalau128 $a1, %pc_hi20(G)
ld.w $a2, $a1, %pc_lo12(G)

```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128427/new/

https://reviews.llvm.org/D128427